Exponential Technology, Inc.

Intel Corporation

Frederick Buckley, Iii

James S Blomgren

Paul Hildebrant

Siegfried Wiedmann

A bandgap voltage reference circuit and related method characterized in having a first current source for generating a first current having a positive temperature coefficient, a second current source for generating a second current having a negative temperature coefficient, and a resistive element to receive both the first and second current to develop a reference voltage. By configuring the circuit such that the magnitudes of the positive and negative temperature coefficients are substantially the same, the reference voltage becomes substantially invariant with changes in temperature. Another circuit is provided in conjunction with the voltage reference circuit to substantially equalize the drain-to-source voltage of the transistors used in the voltage reference circuit.

Current bandgap voltage reference circuits and related methods

A bi-planar multi-chip package has die mounted on both sides of an insulating flexible carrier. The die are located in two parallel planes, with the flexible carrier located on a third plane between the two die planes. The die are mounted with the active circuit area facing each other on opposing sides of the flexible carrier. The carrier has conductive layers forming interconnect traces on both sides, and through-vias for connecting traces on opposite sides. The opposing die are mounted to the carrier with a solder-bump process with opposing pads located directly opposite each other. Vias are located in close proximity to the pads, between adjacent pads on the flexible carrier. Because the vias are between two adjacent pads, the interconnect length between two pads is on the order of the pad pitch. Thus opposing pads on the two die may be connected through the adjacent via with a small interconnect length.

Bi-planar multi-chip module

A static RAM memory is ideally suited for BiCMOS processes. As in standard CMOS memory cells, the cells have cross-coupled inverters that have more efficient n-channel transistors for the drive transistors, which pull a bit line low during a read operation. The weaker p-channel transistors are used for load transistors in the cross-coupled inverters, adding to cell stability while requiring no power. In contrast to prior-art cells, p-channel pass transistors are used. Common-emitter word-line drivers are also used that require a small input-voltage swing in comparison with the large word-line voltage swing. A low voltage on the word line selects a memory cell by causing p-channel pass transistors to conduct, coupling bit lines to the cross-coupled inverters in the memory cell. Power consumption is reduced since only one selected word line is at a low voltage, while the deselected word lines are at a high voltage. Common-emitter word-line drivers have a conduction path from the positive supply terminal to ground when the output word line is low, but no conduction path when the output word line is high. Thus only the common-emitter word-line driver that is connected to the selected low word line consumes appreciable power.

Growing community of inventors

San Jose, CA, United States of America

Frederick Buckley, Iii