Cypress Semiconductor Corporation

Silicon Magnetic Systems

Longitude Flash Memory Solutions Ltd.

Frederick B Jenne

Krishnaswamy Ramkumar

Sagy Charel Levy

Gary Austin Gibbs

Venkatraman Prabhakar

Sam G Geha

Kamel Ounadjela

Galen E Stansell

K Nirmal Ratnakumar

Ken Fox

Oindrila Ray

Igor Kouznetzov

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

SONOS ONO stack scaling

A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region

A nonvolatile trapped-charge memory device and method of fabricating the same are described. Generally, the memory device includes a tunneling layer on a substrate, a charge trapping layer on the tunneling layer, and a blocking layer on the charge trapping layer. The tunneling layer includes a nitrided oxide film formed by annealling an oxide grown on the substrate using a nitrogen source. The tunneling layer comprises a first region proximate to the substrate, and a second region proximate to the charge trapping layer, and wherein the nitrogen concentration decreases from a first interface between the second region and the charge trapping layer to a second interface between the first region and the substrate to reduce nitrogen trap density at the second interface. Other embodiments are also described.

Nitridation oxidation of tunneling layer for improved SONOS speed and retention

A method of fabricating a memory device is described. Generally, the method includes: forming a tunneling layer on a substrate; forming on the tunneling layer a multi-layer charge storing layer including at least a first charge storing layer comprising an oxygen-rich oxynitride overlying the tunneling layer, and a second charge storing layer overlying the first charge storing layer comprising a silicon-rich and nitrogen-rich oxynitride layer that is oxygen-lean relative to the first charge storing layer and comprises a majority of charge traps distributed in the multi-layer charge storing layer; and forming a blocking layer on the second oxynitride layer; and forming a gate layer on the blocking layer. Other embodiments are also described.

Oxide-nitride-oxide stack having multiple oxynitride layers

The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value.

1T smart write

A programmable latch circuit () can include a programmable data circuit () with a data load path () that can enable a data value to be recalled into a volatile latch (). A data load path () can be formed with devices (P-P) having low threshold voltages. Data can be loaded via data load path at lower power supply voltages levels, such as on power-on and/or reset operations. Other embodiments disclose, self-test circuits, full redundancy capabilities, and resistors for limiting current draw in an anti-fuse program operation.

Anti-fuse latch circuit and method including self-test

A magnetic memory array with an improved word line configuration is provided. In some embodiments, the magnetic memory array may be adapted to selectively supply voltage from a single source line to one or more transistors arranged within a first row of the magnetic memory array and to one or more transistors arranged within a second row of the magnetic memory array. In addition or alternatively, the magnetic memory array may be configured to enable current flow along a single current path through a magnetic junction and along multiple paths extending from the single current path to a plurality of transistors. In some embodiments, the plurality of transistors may be formed from a contiguous conductive structure comprising the word line. In some cases, the word line may be configured to include at least two transistors that share a common diffusion region.

Magnetic memory array with an improved world line configuration

A memory array configuration is provided that includes a plurality of magnetic cell junctions and a conductive line comprising a gate of a first transistor configured to enable a read operation for one of a plurality of magnetic cell junctions and a gate of a second transistor configured to enable a write operation for another of the plurality of magnetic cell junctions. Another memory array configuration is provided which includes a set of conductive structures serially coupled to a bit line spaced apart from and, in some embodiments, directly above a magnetic cell junction, a transistor coupled to the set of conductive structures and a program line collectively configured with the bit line to induce current flow through the set of conductive structures upon an application of a voltage to a gate of the transistor. A method for operating such a magnetic memory array is also contemplated herein.

Magnetic memory array configuration

A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.

SONOS structure including a deuterated oxide-silicon interface and method for making the same

A semiconductor topography is provided which includes a magnetic field shield layer formed upon a semiconductor device. In particular, the semiconductor topography may include a ferromagnetic layer adapted to shield underlying layers from external magnetic fields. Such a ferromagnetic layer may include either ferrite and/or non-ferrite materials. In some embodiments, the semiconductor topography may include a magnetic field shield layer with a different pattern configuration than an adjacent passivation layer. Consequently, a method for processing a semiconductor topography which includes patterning a magnetic field shield layer to form openings other than bond pad openings within the semiconductor topography is provided.

Die surface magnetic field shield

A magnetic memory cell and method for improving the write selectivity of memory cells in an MRAM array is provided herein. In particular, the magnetic memory cell may have a magnetic layer with a shape that is substantially asymmetrical about at least one axis of the magnetic layer. Such asymmetry may advantageously reduce and/or eliminate the effects of variations in the fabrication process. In addition, an asymmetrical memory shape may induce a relatively consistent equilibrium vector state, allowing a single switching mechanism to set the magnetic direction of the cell. Furthermore, a method is provided for programming a memory cell, in which the amount of current needed during a writing procedure is advantageously reduced relative to the amount of current needed in conventional writing procedures. In this manner, the asymmetrical memory cell and method produces a storage medium having overall power requirements less than those associated with symmetrical memory cells.

Asymmetric dot shape for increasing select-unselect margin in MRAM devices

The state of a memory cell is stored by selectively imbalancing threshold voltages of storage elements of the memory cell. The threshold voltages may be selectively imbalanced by pulsing the supply voltage for the memory cell from an operating voltage level to a programming voltage level. This may be accomplished by raising the supply voltage from the operating voltage level to the programming voltage level for a period of time sufficient to store the state of the memory cell by monitoring the leakage current from the programming voltage level such that it just falls below a preestablished limit. Alternatively, the supply voltage may be repeatedly toggled between the operating voltage level and the programming voltage level for fixed time intervals until the state of the memory cell is stored. The number of toggling operations may be determined by monitoring the leakage current such that it just falls exceeds a predetermined limit. The programming voltage level may be approximately twice the operating voltage level or greater. Selectively imbalancing the threshold voltages of the storage elements may be accomplished by creating a first electric field within a first of the storage elements to tunnel electrons off of a floating gate of the first storage element and creating a second electric field within a second of the storage elements to inject the electrons onto a floating gate of the second storage element. Preferably, these electric fields are created simultaneously by applying the programming voltage to the memory cell.

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Mountain House, CA, United States of America

Frederick B Jenne