Rambus Inc.

Flex Logix Technologies, Inc.

Hewlett-packard Company

Hefei Reliance Memory Limited

Other

Analog Devices,inc.

Weitek Corporation

Intel Corporation

Cadence Design Systems, Inc.

Lattice Semiconductor Corporation

Highlands Corporation

Rambus Lnc.

Rampart Asset Management, LLC

Frederick Abbott Ware

Craig Edward Hampel

Ely K Tsern

John Eric Linstadt

Richard E Perego

Richard Maurice Barth

Donald C Stark

Thomas Vogelsang

Kenneth Lee Wright

Scott C Best

Suresh Rajan

Ian P Shaeffer

Brent Steven Haukness

John Wood Poulton

Mark A Horowitz

Paul G Davis

Lawrence Lai

Robert E Palmer

Wayne S Richardson

Yuanlong Wang

Matthew Murdy Griffin

John Bradly Dillon

Abhijit Mukun Abhyankar

Kishore Ven Kasamsetty

Brian S Leibowitz

Carl William Werner

Wayne Frederick Ellis

Jared L Zerbe

James Edward Harris

Akash Bansal

Cheng C Wang

Thomas J Giovannini

Amir Amirkhany

David Nguyen

James A Gasbarro

Bret G Stott

Gary Bela Bronner

Dinesh D Patil

Billy Wayne Garrett, Jr

Chad A Bellows

Andrew M Fuller

Jade M Kizer

Michael P Farmwald

Deepak Chandra Sekar

Bradley A May

William N Ng

Hongzhong Zheng

Stefanos Sidiropoulos

Christopher Haywood

John M Wilson

Liji Gopalakrishnan

Kambiz Kaviani

Todd W Bystrom

Farrukh Aquil

Catherine Yuhjung Chen

Kevin S Donnelly

Mohammad Hekmat

Steven Cameron Woo

John Welsford Brooks

Lei Luo

J James Tringali

John Cronan Eble, Iii

Paul Damian Franzon

Thomas J Sheffler

Richard DeWitt Crisp

Yoshihito Koya

John Girdner Atwood, Jr

Michael Raymond Miller

Zhichao Lu

Trung Am Diep

Pradeep Batra

Holden Jessup

Torsten Partsch

Collins Williams

Srinivas Nimmagadda

Valentin Ossman

John G Atwood

Andrew V Anderson

Ming Chu Li

Peter D MacWilliams

Thomas J Holman

Richard E Warmke

Paul Michael Farmwald

Donald R Mullen

Nancy David Dillon, Legal Representative

Karnamadakala Krishnamohan

Timothy Chang

Catherine Chen

Venu Madhav Kuchibhotla

Angus William McLaren

Kyung Suk Oh

Farshid Aryanfar

Patrick R Gill

Vlad Fruchter

Reza Navid

Evan Lawrence Erickson

Chi-Ming Yeung

Kurt T Knorpp

Ramprasad Satagopan

Marc Alan Evans

The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules

A memory system employs an addressing scheme to logically divide rows of memory cells into separate contiguous regions, one for data storage and another for error detection and correction (EDC) codes corresponding to that data. Data and corresponding EDC codes are stored in the same row of the same bank. Accessing data and corresponding EDC code in the same row of the same bank advantageously saves power and avoids bank conflicts. The addressing scheme partitions the memory without requiring the requesting processor to have an understanding of the memory partition.

Energy-efficient error-correction-detection storage

A memory controller includes an interface to couple to storage class memory (SCM) space and dynamic random access memory (DRAM) space. At least a portion of the DRAM storage space is configured as a cache for the SCM storage space. The interface to receive an incoming tag address for a read operation. Tag comparison circuitry performs a comparison of the incoming tag address to stored tag addresses associated with the DRAM cache. The data in the addressed DRAM cache space is selectively provided directly to the memory controller as first read data based on the results of the comparison.

Memory system with cached memory module operations

A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

Configurable, power supply voltage referenced single-ended signaling with ESD protection

A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

Memory system with error detection

In a microprocessor having an instruction execution unit and first and second sets of process execution resources, context information for a process next-to-be-executed by the instruction execution unit is loaded into a register file, translation lookaside buffer and first-level data cache of the first set of process execution resources during a first interval. During the first interval and concurrently with the loading of context information for the process next-to-be executed, the instruction execution unit executes a current process, including accessing context information for the current process within the register file, translation lookaside buffer and first-level data cache of the second set of process execution resources.

Stall-driven multi-processing

Improvements are disclosed for 'leveling' or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK' and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

Memory system with activate-leveling method

A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

Low latency memory access

Disclosed is a memory system including a memory component having at least one tag row and at least one data row and multiple ways to hold a data group as a cache-line or cache-block. The memory system includes a memory controller that is connectable to the memory component to implement a cache and operable with the memory controller and the memory component in each of a plurality of operating modes including a first and second operating mode having differing addressing and timing requirements for accessing the data group. The first operating mode having placement of each of at least two ways of a data group in differing rows in the memory component, with tag access and data access not overlapped. The second operating mode having placement of all ways of a data group in a same row in the memory component, with tag access and data access overlapped.

System application of DRAM component with cache mode

Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Optimizing power in a memory device

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

Memory systems, modules, and methods for improved capacity

A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Memory controller operable in data loop-back mode

An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.

Variable memory access granularity

A cascaded memory system includes a memory module having a primary interface coupled to a memory controller via a first communication channel and a secondary interface coupled to a second memory module via a second communication channel. The first memory module buffers and repeats signals received on the primary and secondary interfaces to enable communications between the memory controller and the secondary memory module.

Cascaded memory system

A lateral transfer path within an adjustable-width signaling interface of an integrated circuit component is formed by a chain of logic segments that may be intercoupled in different groups to effect the lateral data transfer required in different interface width configurations, avoiding the need for a dedicated transfer path per width configuration and thereby substantially reducing number of interconnects (and thus the area) required to implement the lateral transfer structure.

Area-efficient, width-adjustable signaling interface

Growing community of inventors

Los Altos Hills, CA, United States of America

Frederick Abbott Ware