Hewlett-Packard Development Company, L.p.

Frederick A Pemer

Kenneth Kay Smith

Richard Lee Hilton

Stewart R Wyatt

Corbin L Champion

A logical data block in a MRAM is disclosed. The logical data block comprises magnetic memory cells formed at intersections of hard-axis generating conductors and an easy-axis generating conductor. The logical data block may further be configured in size by a preselected, block-based error correction code. A magnetic memory module and computer system including a MRAM having a logical data block according to embodiments of the present invention are also disclosed. Additionally, a method embodiment of reducing half-select write errors within a MRAM is disclosed.

Logical data block, magnetic random access memory, memory module, computer system and method

A data storage device that includes a memory cell string. The memory cell string includes a first memory cell and a second memory cell. The device also includes a circuit coupled to a node between the first memory cell and a second memory cell. The circuit is configured to detect a voltage change at the node in response to a voltage being provided to the memory cell string and the first memory cell being written to a first state.

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Palo Alto, CA, United States of America

Frederick A Pemer