Scintera Networks, Inc.

Xignal Technologies Ag

Frederic Roger

Qian Yu

Armando C Cova

Adric Quade Broadwell

A cost function generator circuit includes memory terms each receiving one or more input signals, and each providing inphase and quadrature output current signals. The inphase and quadrature output currents of the memory terms are summed to provide combined inphase and quadrature output currents, respectively. Transimpedance amplifiers are provided to transform the combined inphase and quadrature output currents into an inphase output voltage and a quadrature output voltage.

Scalable cost function generator and method thereof

Systems and methods are provided for power measurement of signals such that the power measurement is insensitive to PVT variations of the measurement systems. A power measurement system includes an analog squarer circuitry, an integrating ADC, and a controller. The squarer circuitry calculates the power of a signal whose power is to be measured while the integrating ADC integrates the calculated power over a runup interval to generate an integrated power. The squarer circuitry also calculates the power of a reference for the integrating ADC to de-integrate the integrated power over a rundown interval. The power measurements are independent of PVT variations of the analog squarer circuitry and integrating ADC. The controller digitally controls the runup interval and measures the rundown interval to provide digitized power measurements. The analog squarer circuitry have replica squarer circuits. Process dependent mismatches between the replica analog circuitry may be removed through a calibration process.

True RMS power measurement

A performance monitor for generating a digital error signal based upon an RF input signal and an amplified RF output signal is provided. The monitor includes: a first analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase (Q) version of the RF input signal responsive to a first clock signal to provide a first digital I signal and a first digital Q signal; a second analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase version of the amplified RF output signal responsive to a second clock signal to provide a second digital I signal and a second digital Q signal; a first adaptive delay filter to delay the first digital I signal and the first digital Q signal to provide a first delayed complex signal according to a first delay; a second adaptive filter to delay the second digital I signal and the second digital Q signals to provide a second delayed complex signal according to a second delay; a complex gain matching adder operable to add a complex gain matching factor to a selected one of the delayed complex signals to provide a gain matched complex signal; and an adder to add the gain matched complex signal to a remaining one of the first and second delayed complex signals to provide the digital error signal.

Error signal formation for linearization

A high-order harmonics generator includes a plurality of high-pass filters to block out DC signals. In one embodiment, high-pass filters are coupled to the output signals from an envelope detector and a power detector. A high-pass filter can also be coupled to the output of a multiplier that multiplies the filtered envelope signal and the filtered power signal. Additional multipliers may also be used at outputs of multipliers in a cascaded chain of multipliers for higher harmonics generation.

High order harmonics generator

An RF squarer circuit comprises a first RF multiplier and a first variable gain transimpedance amplifier (TIA). The first RF multiplier receives an RF input signal RFIN and provides a first output current. The first TIA receives the first output current as an input. The first TIA provides an output voltage VOUT.

RF squarer

The invention pertains to a circuit arrangement (comparator) for the discrete-time comparison of input signals (ip, vrefp) and for making available a pair of complementary output levels (vdd, vss) which corresponds to the result of the comparison on a line pair (P, N), wherein said circuit arrangement comprises a reset circuit () for balancing the line potentials during a reset phase, an input circuit () for generating a potential difference on the line pair (P, N) in accordance with an input signal difference, a first bistable flip-flop () for amplifying the generated potential difference and a second bistable flip-flop () that is connected by means of a connecting circuit () and serves for additionally amplifying the generated potential difference to the desired complementary output levels. According to the invention, a third bistable flip-flop () is provided that, when connecting the second flip-flop () parallel to the first flip-flop (), amplifies the generated potential difference and thusly reduces the comparison time without significantly impairing the current consumption.

Growing community of inventors

Santa Clara, CA, United States of America

Frederic Roger