Synopsys, Inc.

Other

Frederic Maxime Emirian

Ludovic Marc Larzul

Sebastien Delerse

Luc M Burgun

Embodiments relate to the emulation of circuits, and tracking states of signals in an emulated circuit for performing power analysis. A host system incorporates power analysis logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated power analysis logic. Based on the power analysis logic, during a power analysis clock cycle, the emulator selects a signal from a plurality of signals of the DUT. The emulator determines whether a state event is detected for the selected signal. If the state event is detected, a state count is updated for the selected signal that indicates a number of state events detected for the selected signal during emulation of the DUT. If the state count reaches a threshold number based on the update, the emulator transmits a count update signal to the host system indicating that the state count reached the threshold number.

Efficient power analysis

A method for generating a circuit description for a multi-die field-programmable gate array, FPGA, comprising a first FPGA die and at least one further FPGA die is described. The method is performed in an FPGA design tool and comprises automatically evaluating a first and a second partition of a partitioned circuit description, the partitions being associated with respective ones of the FPGA dies. At least one multiplexing element is inserted into the first partition and a corresponding de-multiplexing element is inserted into the second partition based on the automated evaluation.

Generating a circuit description for a multi-die field-programmable gate array

Embodiments relate to the emulation of circuits, and detecting an event in a plurality of signals in an emulated circuit. A host system incorporates global event detection logic into a design under test (DUT). An emulator emulates the DUT along with the incorporated global event detection logic. The global event detection logic divides one clock cycle of the DUT into multiple time periods. During each time period of the clock cycle, the emulator selects a different subset of signals from the plurality of signals of the DUT. The emulator determines whether an event occurred for a signal from the subset during the clock cycle. If an event is detected, the emulator generates an output indicating an event was detected among the plurality of signals.

Efficient event detection

An apparatus is programmed to automatically remove timing hazards from a circuit design. The apparatus identifies certain level sensitive storage circuit elements in the circuit design. The identified level sensitive storage circuit elements are those having timing hazards. The timing hazards arise as a result of potential skews between the reference signal for the circuit design and the synchronization signal controlling each storage circuit element. A skew, introduced by a gated or divided clock, cannot be assured to be within a design tolerance limit. Therefore, the program enables the apparatus to transform the identified level sensitive storage circuit elements into level sensitive storage circuit elements controlled by synchronization signals that do not have potential skews with respect to the reference signal of the circuit design. The transformation, however, is accomplished without altering the functionality of the circuit design. In effect, the apparatus automatically removes some or all of the timing hazards by determining the appropriate transformation for each of the identified level sensitive storage circuit elements.

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Antony, France

Frederic Maxime Emirian