Imec Vzw

Tokyo Electron Limited

Frederic Lazzarino

Victor M Blanco

Tatsuya Yamaguchi

Koichi Yatsuda

Yannick Feurprier

Jean-Francois De Marneffe

Khashayar Babaei Gavan

Guillaume Bouche

Boon Teik Chan

Juergen Boemmels

Silvia Armini

Sandip Halder

Waikin Li

Danilo De Simone

Shreya Kundu

According to an aspect there is provided a patterning method comprising:

Patterning method

A method of etching an indium gallium zinc oxide (IGZO) structure is provided. In one aspect, the method includes exposing the IGZO structure to a reactant flow including a hydrocarbon-based reactant. Thereby, a reactant layer is formed on the IGZO structure. The method also includes exposing the reactant layer formed on the IGZO structure to an argon flow. Thereby, one or more reactant molecules are removed from the reactant layer. The one or more reactant molecules, which are removed from the reactant layer formed on the IGZO structure, are removed together with one or more IGZO molecules, thus leading to an etching of the IGZO structure.

Method of etching an indium gallium zinc oxide (IGZO) structure

A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses a layer stack comprising three memorization layers: an upper memorization layer allowing first memorizing upper trenches, and then one or more upper blocks; an intermediate memorization layer allowing first memorizing intermediate trenches and one or more first intermediate blocks, and then second intermediate blocks and intermediate lines; and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.

Semiconductor device manufacturing method

A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses one or more first upper blocks formed by a tone-inversion approach, an upper memorization layer allowing first memorizing upper trenches, and then second upper blocks, and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

A method for forming an interconnection structure for a semiconductor device is provided. The method includes: (i) forming a conductive layer on an insulating layer; (ii) forming above the conductive layer a first set of mandrel lines of a first material; (iii) forming a set of spacer lines of a second material different from the first material, wherein the spacer lines of the second material are formed on sidewalls of the first set of mandrel lines; (iv) forming a second set of mandrel lines of a third material different from the first and second materials, wherein the second set of mandrel lines fill gaps between spacer lines of the set of spacer lines; (v) cutting at least a first mandrel line of the second set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the second set of mandrel lines selectively to the set of spacer lines and the first set of mandrel lines, cutting at least a first mandrel line of the first set of mandrel lines into two line segments separated by a gap by etching said first mandrel line of the first set of mandrel lines selectively to the set of spacer lines and the second set of mandrel lines; (vi) removing the set of spacer lines, selectively to the first and second sets of mandrel lines, thereby forming an alternating pattern of mandrel lines of the first set of mandrel lines and mandrel lines of the second set of mandrel lines; and (vii) patterning the conductive layer to form a set of conductive lines, wherein the patterning comprises etching while using the alternating pattern of mandrel lines of the first and second sets of mandrel lines as an etch mask.

Method for forming an interconnection structure

A method for producing a pattern of features on a substrate may involve performing two exposure steps on a resist layer applied to the substrate, followed by a single etching step. In the two exposures, the same pattern of mask features is used, but with possibly differing dimensions and with the pattern applied in the second exposure being shifted in position relative to the pattern in the first exposure. The shift, lithographic parameters, and/or possibly differing dimensions are configured such that a number of resist areas exposed in the second exposure overlap one or more resist areas exposed in the first exposure. When the pattern of mask features is a regular 2-dimensional array, the method produces of an array of holes or pillars that is denser than the original array. Varying the mask patterns can produce different etched structure shapes, such as a zig-zag pattern.

Method for producing a pattern of features by lithography and etching

An example embodiment includes a patterning method comprising: forming a layer stack comprising a target layer, a lower memorization layer and an upper memorization layer, forming above the upper memorization layer a first mask layer, patterning a set of upper trenches in the upper memorization layer, forming a first block pattern, the first block pattern comprising a set of first blocks, patterning a first set of lower trenches in the lower memorization layer, patterning the patterned upper memorization layer to form a second block pattern comprising a set of second blocks, forming above the patterned lower memorization layer and the second block pattern a second mask layer, patterning a second set of lower trenches in the patterned lower memorization layer, the patterning comprising using the second mask layer, the spacer layer and the second block pattern as an etch mask.

A method is provided for patterning a target layer, the method comprising: (i) forming above the target layer a line mask and a mandrel mask, wherein forming the line mask comprises forming parallel material lines extending in a longitudinal direction, wherein forming the mandrel mask comprises forming a mandrel mask having sidewalls including at least a first sidewall extending transverse to a plurality of the material lines; (ii) forming on the sidewalls of the mandrel mask a sidewall spacer including a first sidewall spacer portion extending along the first sidewall; (iii) partially removing the sidewall spacer such that a remainder of the sidewall spacer comprises at least a part of the first sidewall spacer portion; and (iv) subsequent to removing the mandrel mask, transferring into the target layer a pattern defined by the line mask and the remainder of the sidewall spacer.

Patterning a target layer

The present disclosure provides a method for defining patterns for conductive paths in a dielectric layer. An example method includes forming a mask layer and forming a set of mandrels, each mandrel having a pair of side wall spacers. The method also includes etching the mask layer to form a first set of trenches in the mask layer. The method further includes covering the set of mandrels with a metal oxide planarization layer, the metal oxide planarization layer filling the first set of trenches. The method also includes etching back the metal oxide planarization layer. The method also includes removing the set of mandrels by etching, thereby forming trenches in the metal oxide planarization layer, the trenches extending between the pairs of side wall spacers. The method also includes etching the mask layer to form a second set of trenches in the mask layer.

Method for defining patterns for conductive paths in dielectric layer

An example embodiment may include a method for defining patterns for conductive paths in a dielectric layer. The method may include (a) forming a mask layer on the dielectric layer, (b) forming on the mask layer a set of longitudinally and parallel extending mask features, each mask feature including a mandrel having a pair of side wall spacers, the mask features being spaced apart such that gaps are formed between the mask features, (c) depositing an organic spin-on layer covering the set of mask features and filling the gaps, (d) etching a first trench in the organic spin-on layer, the first trench extending across at least a subset of the gaps and exposing the mask layer, and (e) depositing in a spin-on process a planarization layer covering the organic spin-on layer and filling the first trench.

Method for defining patterns for conductive paths in a dielectric layer

A method is provided for fabricating a semiconductor device that includes providing a structure with a sacrificial layer having at least one through-hole exposing a metal surface and, optionally, an oxide surface. In one example, the method may include applying a self-assembled monolayer selectively on the exposed metal surface and/or on the oxide surface. The method may also include growing a metal on the self-assembled monolayer and on the exposed metal surface if no self-assembled monolayer is present thereon, so as to fill the at least one through-hole, thereby forming at least one metal structure. The method may further include replacing the first sacrificial layer by a replacement dielectric layer having a dielectric constant of at most 3.9.

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Hamme-Mille, Belgium

Frederic Lazzarino