Broadcom Corporation

Koninklijke Philips Corporation N.v.

Vlsi Technology, Inc.

Frederic Hayem

Louis Botha

Leo Borromeo

Andrew Du Preez

Johan (Hendrik) Conroy

Michiel Petrus Lotter

Michiel Lötter

Patrick Arnould

Hendrik Johannes Conroy

A multi-mode wireless communication device and multi-mode communication method are disclosed. The multi-mode device includes a first baseband co-processor configured to execute low-level stack operations of a first wireless communications protocol employed within a first wireless communications network. The device also includes a host baseband processor configured to execute a set of protocol stack operations of a second wireless communications protocol employed within a first wireless communications network and higher-level stack operations of the first wireless communications protocol. A data communication channel capable of carrying data received by the multi-mode wireless communication device from the first wireless communications network or sent by the multi-mode wireless communication device through the first wireless communications network is provided between at least the host baseband processor and the first baseband co-processor.

Multi-processor platform for wireless communication terminal having a partitioned protocol stack

A multi-mode communication device is disclosed and includes a host baseband processor configured to operate in a first communications system of a plurality of communications systems, and a baseband co-processor configured to operate in a second communications system of the plurality of communications systems. The second communications system is different from the first communications system. The host baseband processor is operable to time synchronize the second communications system to the first communications system based on timing information generated by the baseband co-processor. The host baseband processor may include circuitry for issuing, from the host baseband processor, a timer capture interrupt to the baseband co-processor during a predetermined timer phase of the first communications system.

Synchronization of multiple processors in a multi-mode wireless communication device

Multi-processor platform for wireless communication terminal having partitioned protocol stack

Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

Method and system for a RFIC master

A method for operating a Radio Frequency (RF) receiver of a wireless terminal. During a first time interval, an RF front end is enabled and the RF receiver receives and processes an RF signal, e.g., a Wideband Code Division Multiple Access (WCDMA) signal, to produce a baseband signal and to store samples of the baseband signal. During a second time interval that differs from the first time interval, the RF front end is disabled and the RF receiver processes the plurality of samples of the baseband signal of the first time interval to measure signal strengths of a plurality of pilot signals present in the baseband signal of the first time interval. Finally, during a third time interval that differs from the first time interval and the second time interval, the RF front end is enabled and the RF receiver receives and processes an RF signal of the third time interval to extract data there from. Memory is shared between the first, second, and third time intervals for different uses.

Time divided pilot channel detection processing in a WCDMA terminal having a shared memory

A method for effecting timing synchronization within a multi-mode communication device is disclosed herein. The method includes configuring a host baseband processor of the multi-mode device to operate in accordance with a first wireless communications protocol of a first wireless communications system. A baseband co-processor of the device is also configured to operate in accordance with a second wireless communications protocol of a second wireless communications system. The method includes establishing, within the device, timing synchronization between the first and second communication systems on the basis of timing information transferred to the host baseband processor from the baseband co-processor.

Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.

Method and system for configurable trigger logic for hardware bug workaround in integrated circuits

A method of operating on a net-list describing an integrated circuit design for use with an automated test pattern generator for testing an integrated circuit built using the design is described. The method includes replacing a defective portion of the design in test mode with a substitute circuit to reduce testing impact of the defective portion. The method includes identifying a first defective portion of the integrated circuit design in the net-list, determining conditions under which the first defective portion is likely to malfunction and replacing the first defective portion in the net-list with another first portion that provides unknown output signals representing an unknown state in response to conditions under which the first defective portion is likely to malfunction.

Integrated circuit analysis and design involving defective circuit element replacement on a netlist

The present invention includes a circuit assembly and method of synchronizing plural circuits. According to one aspect of the present invention, a circuit includes: an oscillator configured to generate a reference clock signal; a first circuit including: a first divider configured to generate a first internal clock signal responsive to the reference clock signal; and reset generation circuitry configured to receive an external reset signal and generate a reset second circuit signal synchronized with a predefined position of the first divider, with the reference clock signal and with the external reset signal; and a second circuit including: reset detection circuitry configured to generate a reset detection signal synchronized with the reset second circuit signal and the reference clock signal; and a second divider configured to set to a predefined position responsive to the reception of the reset detection signal and generate a second internal clock signal synchronized with the first internal clock signal.

Growing community of inventors

San Diego, CA, United States of America

Frederic Hayem