Atmel Corporation

Frederic Demolli

Michel Cuenca

Thierry Soude

Daniel Payrard

David Bernard

Antoine Riviere

Didier Davino

Joao Pedro Antunes Carreira

Thierry Soudé

An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.

Threshold voltage method and apparatus for ESD protection

Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is a logarithmic function, where each has a mathematical correlation to a function of the power supply voltage.

Method for providing a power on reset signal with a logarithmic current compared with a quadratic current

Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.

Method for providing a power on reset signal with a quadratic current compared to an exponential current

A low dropout voltage regulator with switching output current boost circuit. In one aspect of the invention, a voltage regulator circuit includes a low dropout voltage regulator providing an output voltage at an output based on an input voltage at an input, and a boost circuit connected to the low dropout voltage regulator. The boost circuit includes a comparator and a boost transistor device for allowing additional current to be provided to the output of the low dropout voltage regulator when the output voltage of the current regulator falls below a predetermined threshold.

Low dropout voltage regulator with switching output current boost circuit

A low-dropout (LDO) voltage regulator for generating an output voltage is disclosed. The voltage regulator includes a startup circuit, a curvature corrected bandgap circuit, an error amplifier, a metal oxide semiconductor (MOS) pass device and a voltage slew rate efficient transient response boost circuit. The MOS pass device has a gate node which is coupled to the output of the error amplifier, and a drain node for generating the output voltage. The voltage slew rate efficient transient response boost circuit applies a voltage to the gate node of the MOS pass device to accelerate the response time of the error amplifier in enabling the LDO voltage regulator to reach its final regulated output voltage when an output voltage drop occurs in the LDO voltage regulator.

Low-dropout voltage regulator with a voltage slew rate efficient transient response boost circuit

A current compensation circuit and an optimized current compensation circuit are disclosed for a Parallel Resistors Architecture (PRA) digital-to-analog converter (DAC). The circuits are used to balance code dependent current consumption of the PRA-DAC.

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Rognac, France

Frederic Demolli