Texas Instruments Corporation

Frederic Danis

Eric Louis Pierre Badi

Francois M Amand

Jean-Yves Carre

Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A first one of the sequence of commands is sent from the queue module via the bus to a target module. The queue module is paused while waiting for a response via the bus from the target module; however, the initiator may continue processing another task. The queue module repeatedly sends a next command via the bus to the target module and waits for a response via the bus from the target module until a last one of the sequence of commands is sent to the target module. The queue module provides only a single acknowledgement to the initiator module after the sequence of commands has been transferred to the target module.

12C bus controller slave address register and command FIFO buffer

I2C controller register, control, command and R/W buffer queue logic

A system and method for automatically determining a type of electrical interface used by a Universal Integrated Circuit Card ('UICC') card. In one embodiment, a wireless device includes a UICC card port, and UICC detector. The UICC detector determines which of a plurality of electrical interfaces are provided by a UICC card coupled to the UICC card port. The UICC detector configures the UICC card port in accordance with a provided electrical interface of the UICC card.

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La Colle sur Loup, France

Frederic Danis