Hewlett-packard Company

Hitachi, Ltd.

Hewlett-packard Development Company, L.p.

Frederic C Amerson

Rajiv Gupta

William S Worley, Jr

Michael S Schlansker

Vinod Kumar Kathail

Paul M Hubel

B Ramakrishna Rau

William R Mason

Chandrakant D Patel

Christian Laszlo Belady

Alan Hersh Karp

Robert M English

Donald J Stavely

Ricardo Jansson Motta

Naohiko Irie

David Kay Campbell

K Douglas Gennetten

Richard J Carter

Charles H McConica

Yooichi Shintani

Susan Hunter

Yoshikazu Tanaka

Bantwal R Rau

Tan Watanabe

Dennis Brzezinski

Balasubramanian Kumar

A method for handling peripheral signals in an extensible three dimensional circuit includes forming an extensible three dimensional circuit with a plurality of stacked crossbar arrays and at least one class of traveling lines which travel vertically and laterally through the circuit. The method also includes alternating the traveling direction of bundles of traveling lines such that there are a substantially equal number of undriven lines and underutilized lines which exit out of a given side of the circuit and creating loopback traces which connect the undriven traveling lines and the underutilized traveling lines to form driven traveling lines with a full complement of memory elements and eliminate addressing gaps within the circuit.

Peripheral signal handling in extensible three dimensional circuits

A digital image capture and processing system, comprising a lens coupled to a lens control element is disclosed. The image capture system includes an image sensor configured to capture images from the lens, and a memory element and a processor coupled to the lens control element. The memory element includes image capture software, where the image capture software causes the lens and the image sensor to capture at least two images, each of the at least two images captured using a varying parameter and stored as a single file where the at least two images are combined to form a new image having at least one characteristic different from corresponding characteristics of the at least two images.

System and method for using multiple images in a digital image capture device

An auxiliary illuminating device that has an adjustable color temperature. The color temperature is adjusted by varying the light output at least two independently adjustable light sources. The light source is an array of at least 2 colors. The light source typically uses at least one set of LED's.

Auxiliary illuminating device having adjustable color temperature

A programmable logic device (PLD) including a plurality of programmable tiles organized in blocks. Each block comprises a unique subset of the plurality of programmable tiles. A data bus extends to each of the blocks. An independent address circuit is provided within each block. A block select line is coupled to each block such that when the block select is line is asserted the address circuit of a selected block is capable of transferring data from the data bus to the plurality of programmable tiles and when the block enable line is deasserted the data bus is substantially electrically isolated from the address circuit and data bus.

Block segmentation of configuration lines for fault tolerant

A low-cost high aspect ratio skived heatsink with high performance ducting in order to optimize airflow over and through the skived fins. The skived heatsink can additionally have formed channels or extruded holes for insertion of a heatsink pipe therein. A thermally enhanced compound is used between the heatsink and heatpipe to provide a low thermal resistance between the parts. The heatpipe is expanded to optimally fill the channel or hole by injecting pressured fluid into the pipe before sealing the pipe with working fluid, or via heating of a sealed pipe and expansion of the working fluid therein. A partitioned cooling system can additionally be used, one partitioned section having high volume airflow with low static pressure, and another partitioned section using higher velocity ducted air over a plurality of skived heatsinks.

Ducted high aspect ratio heatsink assembly

A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file. If an exception is detected, then the exception is processed and one or more of the speculative operation are re-executed (in a non-speculative mode) where necessary to process the exception.

Method and system for propagating exception status in data registers and

To improve the function of a circuit for prefetching data accessed by a processor, a prefetch unit incorporates therein a circuit for issuing a request to read out one group of data to be prefetched and registers for holding the group of data read in response to the read request therein. The group of data are read out from a cache memory or a main memory under the control of a cache request unit. A plurality of groups of data can be prefetched. When data designation is made, the processor requests the cache memory to read a block to which the data to be prefetched belongs. A circuit is also included in the prefetch unit, wherein when prefetched data is subsequently updated by the processor, its updated data is made invalid. Elements of a vector complex in structure, such as an indexed vector or the like can be also read out. It is also possible to cope with an interrupt generated within the processor.

Information processing apparatus with prefetch control for prefetching

A method for supporting speculative execution includes designating operations as speculative or non-speculative, and then deferring exceptions generated by speculative operations while immediately reporting exceptions by non-speculative operations. If a speculative operation uses a result of a speculative operation that has generated an exception, the exception is propagated. Deferred exceptions are detected and reported using a check operation either incorporated into a non-speculative operation or inserted as a separate check operation. A system for supporting speculative execution includes a functional unit for recognizing a speculative operation and deferring any exceptions generated by such an operation. The functional unit may defer an exception by storing information indicating an error has occurred in the register file. To check for deferred exceptions, the functional unit then reads the register file.

Method and system for deferring exceptions generated during speculative

The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.

Vector memory operations

An improved data processing system for executing branch instructions which has lower latency times and which only rarely requires the instruction pipeline to be flushed is disclosed. The data processing system utilizes a register file to hold the information needed to execute a branch instruction. The information is loaded into the register file in advance of the branch instruction. This allows the system to prepare more than one branch instruction at any given time. The present invention may be used to cause the cache line containing the target address of the branch instruction to be loaded soon as the target address is available for the branch instruction. Since the outcome of the branch instruction is almost always known when the branch instruction enters the instruction pipeline, the instruction pipeline only rarely needs to be flushed.

Computer architecture for reducing delays due to branch instructions

In a digital computer, a circular queue of registers in a register file are allocated as temporary local storage for procedures rather than using the known caller/callee save convention in order to minimize main memory references. A called procedure dynamically allocates local registers as needed without regard to registers used by the caller of the procedure or by any callee of the procedure, whereby register allocation is not restricted by any predetermined window size. Local registers, including parameter passing registers, are allocated in the called procedure, rather than a priori at compile time, by adjusting register stack pointer values. Only the number of registers actually required by the procedure need by allocated. Optionally, rotating registers may be allocated among the local registers. Stack pointer values are stored in one of the parameter passing registers when a procedure is called. Hardware register file access circuitry maps virtual register numbers used by the procedures into the hardware register file. Upon return from a procedure, registers are deallocated by adjusting the register stack pointers to the values stored when the procedure was called.

Dynamic allocation of registers to procedures in a digital computer

A memory processor which prevents errors when the compiler advances long latency load instructions in the instruction sequence to reduce the loss of efficiency resulting from the latency time. The memory processor intercepts all load and store instructions prior to the instructions entering the memory pipeline. The memory processor stores load instructions for a period of time sufficient to determine if any subsequent store instruction that would have been executed prior to the load instruction, had the load instruction not been moved, references the same address as that specified in the load instruction. If a store instruction references the load instruction address, the invention returns the same data as the load instruction would have if it was not moved by the compiler.

Growing community of inventors

Santa Clara, CA, United States of America

Frederic C Amerson