Texas Instruments Corporation

Analog Devices,inc.

Mediatek Corporation

Frederic Boutaud

Peter N Ehlig

James F Hollander

Gerard Chauvel

Jason A Jones

Marc Couvrat

Paul D Krivacek

Mansoor A Chishtie

Shigeshi Abiko

Yuji Ozawa

Sean M FitzPatrick

Oliver Mougenot

Joern Soerensen

Palle Birk

Ajay J Padgaonkar

Alain Vallauri

Yves Masse

J&oslash;rn S&oslash;rensen

Sigheshi Abiko

The present invention is directed to methods and apparatus which may be used to help prevent electronic devices, including cell phones, from operating with software copied from (and only authorized for use by or on) another device. A further aspect is a device, including a cell phone, for example, that employs any of such methods and apparatus. Aspects of the present invention compare a program identifier (associated with software stored in a device) to a reference identifier for the device, so as to determine whether the software is authorized for use with that device. Some embodiments respond to the comparison substantially in hardware, so that the software being checked is less able to prevent the device from being disabled in the event that the program identifier and the reference identifier do not match one another.

Method and apparatus for use in securing an electronic device such as a cell phone

A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code discontinuity is encountered, the unified memory is accessed a first time during an instruction cycle with a dummy access. The unified memory is accessed a second time during the instruction cycle when a program code discontinuity is encountered with either a data access, as in the case of a last instruction of a loop, or an instruction access, as in the case of a jump instruction.

Digital signal processor architecture with optimized memory access for code discontinuity

A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Microphone/speaker system with context switching in processor

A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

IC with wait state registers

Described is a system and method for centralized synchronization for the transportation of data between devices in different clock domains. In a preferred embodiment, synchronization logic synchronizes read data from an asynchronous peripheral to a bus clock. Rather than being located on each peripheral, the synchronization logic is located in the bus interface logic. When there is an indication that synchronization is needed for a peripheral, the synchronization logic samples the data bus twice or more and compares the values of consecutive data samples. If the data samples are equal, this data is returned to the bus master. If they are different, the data in the next cycle is returned to the bus master.

Circuit and method for providing centralized synchronization for the transportation of data between devices in a different clock domains on a data bus

A digital signal processing system includes multiple processors, and one or more shared peripherals such as memory. The architecture includes plural bus masters, each connected to its own bus. There are also plural bus slaves, each connected to its own bus. A bus arbitration module selectively interconnects the buses, so that when the plural bus masters each access a different bus slave, no blocking occurs, and when the plural bus masters each access a same bus slave, bandwidth starvation is avoided. The architecture is supported by a bus arbitration method including hierarchical application of an interrupt-based method, an assigned slot rotation method and a round-robin method, which avoids both bandwidth starvation and lockout during extended periods of bus contention. The system further includes a cache memory system allowing one process to perform real-time digital signal processing according to a modifiable program stored in a modifiable non-volatile memory by temporarily loading portions of the program into a fast, local memory.

Cache memory system and method for a digital signal processor

Described is an apparatus and a method for pulling an integrated circuit I/O pad to a known state and providing a current path between the pad and a source of potential during periods when an I/O voltage is likely to be floating. At least one I/O transistor coupled between the I/O pad and a source of potential is provided. Also provided is a combinatorial circuit connected to the I/O transistor to turn on the I/O transistor during periods that the I/O voltage is likely to be floating.

Method and an apparatus to actively sink current in an integrated circuit with a floating I/O supply voltage

Described is a Schmitt trigger cell that can be disabled under conditions of unknown gate voltages (e.g., floating or toggling input) such that the core is isolated from the Schmitt trigger input. This is accomplished by circuitry that disables current flow through those transistors whose gate voltages are unknown during such conditions and that forces a known output onto the output terminal.

Schmitt trigger device with disable

A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.

Glitch free clock select switch

A circuit for interfacing a processor with a host processor is provided that has a memory associated with the processor that is selectively accessible by either both the processors or by the host processor, a plurality of storage devices selectively interconnectable with the memory and host processor, and a logic circuit interconnected with the storage devices and processors for interconnecting at least a portion of the storage devices to the memory in response to signals from the processors. An integrated circuit is provided that has a microprocessor, a memory associated with said processor that is selectively accessible by said microprocessor or a host processor, a plurality of storage devices selectively interconnectable with said memory and said host processor, and a logic circuit interconnected with said storage devices and interconnectable with said processors for interconnecting at least a portion of said storage devices to said memory in response to signals from said processors.

Host port interface

DSP with wait state registers having at least two portions

Digital signal processor with wait state register

Integrated circuit with wait state registers

A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Process of operating a microprocessor to use wait state numbers

A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.

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Roquefort les Pins, France

Frederic Boutaud