Qualcomm Incorporated

Stmicroelectronics S.a.

Frederic Bossu

Prasad Srinivasa Siva Gudem

Gurkanwal Singh Sahota

Dongjiang Qiao

Chiewcharn Narathong

Li Liu

Li-chung Chang

Jingcheng Zhuang

Ojas Choksi

Christian Holenstein

Mahim Ranjan

Tsai-Pi Hung

Kevin H Wang

Jeremy Mark Goldblatt

Steven C Ciccarelli

Junxiong Deng

Gang Zhang

Vijay Chellappa

Xinhua Chen

Yung-Chung Lo

Yiping Han

Jae-Hong Chang

Saru Palakurty

Chang-Ho Lee

Bhushan Shanti Asuri

Vladimir Aparin

Todd Robert Sutton

Aristotele Hadjichristos

Udara Fernando

Yiwu Tang

Aleksandar Miodrag Tasic

Shrenik Patel

Helena Deirdre O'Shea

Sumit Verma

Ravi Sridhara

Wu-Hsin Chen

Jean-Charles Grasset

Chris M Rosolowski

Ahmed Abdel Monem Youssef

Sankaran Aniruddhan

Zixiang Yang

Mark Vernon Lane

Anthony Segoria

Ketan Humnabadkar

Hardik M Patel

Animesh Paul

Jianyun Hu

Minghui Chen

Sriramgopal Sridhara

Wesley Alan Sampson

Berke Cetinoneri

Praveen-Kumar Sampath

Shailesh Shekhar Rai

Vijay K Chellappa

Li-Chung Chang

Ojas M Choksi

Udara C Fernando

Anthony Francis Segoria

A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), a second voltage regulator to regulate a second input voltage to the second voltage regulator, and a switch circuit to selectively activate at least one of the first voltage regulator or the second voltage regulator. In one aspect, the second voltage regulator includes an N-type metal-oxide-semiconductor (NMOS). In one aspect, the second voltage regulator comprises a two-stage operational transconductance amplifier (OTA) circuit. In an aspect, the first voltage regulator is coupled to the second voltage regulator.

On-chip dual-supply multi-mode CMOS regulators

A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.

A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.

Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation

A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.

System-on-a-chip clock phase management using fractional-N PLLs

Techniques for using a narrow filter located before a power amplifier to reduce interference in an adjacent frequency band are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes the narrow filter and the power amplifier. The narrow filter is for a first frequency band (e.g., Band) and has a first bandwidth that is more narrow than the first frequency band. The narrow filter receives and filters an input radio frequency (RF) signal and provides a filtered RF signal. The power amplifier receives and amplifies the filtered RF signal and provides an amplified RF signal. The apparatus may further include a full filter for the first frequency band and located after the power amplifier. The full filter receives and filters the amplified RF signal and provides an output RF signal when it is selected for use.

Wireless device with filters to support co-existence in adjacent frequency bands

A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

PLL post divider phase continuity

An apparatus includes an elliptical inductance-capacitance (LC) filter and a resistive-capacitive (RC) notch filter serially coupled to the elliptical LC filter. The elliptical LC filter and the RC notch filter are configured to filter a radio-frequency (RF) signal received by a feedback receive path.

Feedback receive path with RF filter

Removing common-mode current from a pair of complementary current signals, including: generating a common-mode voltage of the pair of complementary current signals including at least a first current signal and a second current signal; measuring and outputting a difference voltage between the generated common-mode voltage and a common-mode reference voltage; and removing at least a portion of the common-mode current from the first current signal and the second current signal based on the difference voltage.

Transmitter digital-to-analog converter (DAC)-baseband filter (BBF) common mode interface

An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.

Bias techniques and circuit arrangements to reduce leakage current in a circuit

Exemplary embodiments are related to enhancing power efficiency of an electronic device. A device may include a power management module and a radio-frequency (RF) module coupled to the power management module. The device may further include a digital module coupled to each of the power management module and the RF module and configured to dynamically adjust at least one setting of the power management module based on one or more RF conditions.

Dynamic power management control

A wireless communication device configured for receiving a multiple carrier signal is described. The wireless communication device includes a single-chip signal splitting carrier aggregation receiver architecture. The single-chip signal splitting carrier aggregation receiver architecture includes a primary antenna, a secondary antenna and a transceiver chip. The single-chip signal splitting carrier aggregation receiver architecture reuses a simultaneous hybrid dual receiver path.

Single chip signal splitting carrier aggregation receiver architecture

A receiver architecture for carrier aggregation is disclosed. In an exemplary design, an apparatus (e.g., a wireless device, a circuit module, etc.) includes a plurality of low noise amplifiers (LNAs), a plurality of switches, and at least one downconverter. The LNAs receive and amplify at least one input radio frequency (RF) signal and provide at least one amplified RF signal. The switches are coupled to the outputs of the plurality of LNAs. The at least one downconverter is coupled to the plurality of switches, downconverts the at least one amplified RF signal, and provides at least one downconverted signal. The switches reduce the number of downconverters needed to support reception of transmissions on multiple sets of carriers via multiple receive antennas. The LNAs and the switches may be implemented on at least one front-end module or a back-end module. The downconverter(s) are implemented on the back-end module.

Carrier aggregation receiver architecture

Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.

Dynamic reference frequency for fractional-N Phase-Locked Loop

Techniques for calibrating a receiver based on a local oscillator (LO) signal from another receiver are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit) includes first and second local oscillator (LO) generators. The first LO generator generates a first LO signal used by a first receiver for frequency downconversion. The second LO generator generates a second LO signal used by a second receiver for frequency downconversion in a first operating mode. The second LO signal is used to generate a test signal for the first receiver in a second operating mode. The second LO signal may be provided as the test signal or may be amplitude modulated with a modulating signal to generate the test signal. The test signal may be used to calibrate residual sideband (RSB), second order input intercept point (IIP2), receive path gain, etc.

Receiver calibration with LO signal from inactive receiver

Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.

Impedance balancing for transmitter to receiver rejection

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San Diego, CA, United States of America

Frederic Bossu