Motorola Corporation

Frederic B Shapiro

Douglas W Schucker

Robert H Reuss

Gregory Djaja

Steven M Domer

Kendall G Moore

Roger L Hollstein

Michael W Hodel

Timothy J Jennings

Deborah J Beckwith

A sensing circuit (202) uses correlated double sampling to sample a first pixel signal of a pixel stream (V.sub.PIXEL) at two different times to produce a dark signal and a light signal on two capacitors (310, 314). The dark and light signals are amplified in an amplifier (302) to produce a differential output signal (V.sub.PP -V.sub.PN) proportional to their difference. While the samples of the first pixel signal are being amplified, a second pixel signal is double-sampled to produce dark and light signals on two other capacitors (312, 316) for amplifying in the same amplifier. The period of the pixel signal is divided into time slots (T.sub.1 -T.sub.16) by a clocked oscillator (52). Programming signals (PROG1, PROG2) control the time slots in which sampling control pulses (V.sub.S1, V.sub.S2) are generated.

Sensing circuit for capturing a pixel signal

An N-channel JFET (60) and a method of forming the N-channel JFET (60) in a BiCMOS process. The N-channel JFET (60) is monolithically fabricated with an N-channel IGFET (70), a P-channel IGFET (75), and an NPN BJT (80) in an epitaxial layer (21). The N-channel JFET (60) is formed in an isolated N-channel JFET region (24), the P-channel IGFET (75) is formed in an isolated P-channel IGFET region (27), and the NPN BJT (80) is formed in an isolated BJT region (29). The N-channel IGFET (70) is fabricated in a P-type well (26) that is not isolated from other N-channel IGFET's in the epitaxial layer (21). Accordingly, the N-channel JFET (60), the N-channel IGFET (70), the P-channel IGFET (75), and an NPN BJT (80) are monolithically formed in the BiCMOS process.

Method of forming a monolithic semiconductor integrated circuit having

A method for optimization of delay times in a digital circuit. The method comprises selecting a logic gate (12), and constructing a model (35) which predicts the delay time (27) of the logic gate (12). Varying the parameters which control the model to more accurately predict the delay time (48). Summing the delay time (48) due to each logic gate (12) which comprises the signal path. Repeating the method for each signal path within the digital circuit until all signal paths are computed. Modifying the digital circuit based on the calculated delay times (48) so as to better satisfy a predetermined measurement criteria.

Method for optimization of digital circuit delays

A circuit for detecting when a fault condition has occurred includes an input stage responsive to a logic signal supplied to an input of the circuit for providing an output logic signal at an output thereof. An output stage, including a pulldown circuit, responsive to the output logic signal of the input stage, for providing an output logic signal at an output of the circuit. A fault detection circuit coupled to the output of the input stage and to the output stage for forcing the output of the circuit to a predetermined logic state when the pulldown circuit of the output stage is defective.

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Phoenix, AZ, United States of America

Frederic B Shapiro