Mellanox Technologies, Ltd.

Freddy Gabbay

Diego Crupnicoff

Zachy Haramaty

Michael Kagan

Alon Webman

Amiad Marelli

Benny Koren

Miriam Menes

Eitan Zahavi

Gil Bloch

George Elias

Itamar Rabenstein

Ido Bukspan

Oded Zemer

Noam Katz Abramovich

Ido Bukshpan

Shimon Rottenberg

Noam Bloch

Barak Gafni

Shachar Raindel

Zachy Hamamaty

Eilan Rabin

Haggai Telem

A method for communication, includes routing unicast data packets among nodes in a network using respective Layer-3 addresses that are uniquely assigned to each of the nodes. Respective Layer-2 unicast addresses are assigned to the nodes in accordance with an algorithmic mapping of the respective Layer-3 addresses. The unicast data packets are forwarded within subnets of the network using the assigned Layer-2 addresses.

Simplified packet routing

A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.

Packet switch with reduced latency

A method includes receiving in a network switch of a communication network communication traffic that originates from a source node and arrives over a route through the communication network traversing one or more preceding network switches, for forwarding to a destination node. In response to detecting in the network switch a compromised ability to forward the communication traffic to the destination node, a notification is sent to the preceding network switches. The notification is to be consumed by the preceding network switches and requests the preceding network switches to modify the route so as not to traverse the network switch.

Adaptive routing using inter-switch notifications

An apparatus includes multiple data sources and arbitration circuitry. The data sources are configured to send to a common destination data items and respective arbitration requests, such that the data items are sent to the destination regardless of receiving any indication that the data items were served to the destination in response to the respective arbitration requests. The arbitration circuitry is configured to receive and buffer the data items, to perform arbitration on the buffered data items responsively to the arbitration requests, and to serve the buffered data items to the destination in accordance with the arbitration.

Credit based low-latency arbitration with data transfer

Methods and systems are disclosed for network congestion management. The methods and systems receive a first packet complying with a first network protocol comprising a first congestion indicator representative of a presence or absence of network congestion and further comprising a first set of data associated with a second network protocol, and provide an indication of the presence or absence of network congestion generated based, at least in part, on the first congestion indicator. The methods and systems also receive a first packet complying with a first network protocol comprising a first set of data associated with a second network protocol, and output a second packet complying with the first network protocol comprising a first congestion indicator representative of a presence of network congestion.

Methods and systems for network congestion management

A method includes receiving in a network element a packet, which includes a delay field that indicates an overall time delay accumulated by the packet until arriving at the network element. Upon receiving the packet, an interim value is substituted in the delay field. The interim value is indicative of a difference between the overall time delay and an arrival time of the packet at the network element. Before sending the packet from the network element, the overall time delay is updated in the delay field based on the interim value and on a departure time at which the packet is to exit the network element. The packet, including the updated overall time delay, is transmitted from the network element.

Direct updating of network delay in synchronization packets

A method and apparatus for conveying data over a packet-switching network (). Data are received from a peripheral device () for transmission via the network to a memory () associated with a central processing unit (CPU) (), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface () serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

Synchronization of interrupts with data packets

A method for link-level flow control includes establishing a plurality of logical links over a physical link between a transmitting entity and a receiving entity in a network. Respective maximum limits of transmission credits are assigned to the logical links, the credits corresponding to space available to the links in a dynamically allocable portion of a receive buffer at the receiving entity, such that a sum of the maximum limits for all of the logical links corresponds to an amount of space substantially larger than a total volume of the space in the dynamically allocable portion of the receive buffer. Responsive to traffic from the transmitting entity to the receiving entity on a given one of the logical links, one or more of the credits are allocated to the given logical link when it is determined that a total of the credits allocated to the given logical link is no greater than the respective maximum limit, and that a total of the credits allocated to all of the logical links together corresponds to an allocated volume that is no greater than the total volume of the space in the dynamically allocable portion of the receive buffer. Transmission of data over the given logical link is controlled responsive to the allocated credits.

Packet communication buffering with dynamic flow control

A bridge device, for coupling a parallel bus to a packet network, includes a bus interface adapter, coupled to the parallel bus so as to receive bus cycles from a master device on the bus. An outbound packet register, having a bus address in an address space of the bus, is adapted to store an outbound network address header and payload data written to the bus address of the register by the master device in one or more of the bus cycles received by the bus interface adapter. A network interface adapter is coupled to the network so as to transmit over the network an outbound packet containing the outbound network address header and payload data from the register, to a target device on the network specified by the network address header.

Software interface between a parallel bus and a packet network

A device for switching packets in a network includes a switching core and a plurality of ports, coupled to pass the packets from one to another through the switching core. The ports include, with respect to each packet among the packets switched by the device, a receiving port, coupled to receive the packet from a packet source, and a destination port, to which the packet is passed for conveyance to a packet destination. The ports also include one or more cache memories, respectively associated with one or more of the ports, each of the cache memories being configured to hold a forwarding database cache for reference by the receiving port with which the cache memory is associated in determining the destination port of the packet.

Forwarding database cache

A method and apparatus for conveying data over a packet-switching network. Data are received from a peripheral device for transmission via the network to a memory associated with a central processing unit (CPU), followed by an interrupt signal from the peripheral device associated with the data. One or more data packets containing the data are sent over the network to a host network interface serving the memory and the CPU, followed by an interrupt packet sent over the network to the host network interface. Responsive to the interrupt packet, an interrupt input of the CPU is asserted only after the one or more data packets have arrived at the host network interface.

Growing community of inventors

Givataim, Israel

Freddy Gabbay