France Telecom

Freddy Balestro

Patrice Senn

Gregoire Le Tourneur

Alain Wittmann

A device for programmable delay of an analog signal in an acoustic antenna that comprises at least one analog/digital converter circuit delivering, from the analog signal, a digital signal at a first sampling frequency, followed by a delay memory receiving the digital signal in write mode, making it possible to store M consecutive samples in memory. A circuit for write and read access to the delay memory is provided to address the delay memory in write and read mode, which, under read access control, delivers a series of samples delayed by a defined value, a function of the number of samples M stored therein. A sub-sampling circuit receives the delayed digital signal and delivers a sub-sampled delayed digital signal at a second sampling frequency less than the first sampling frequency.

Device for programmable delay of an analog signal and corresponding

The device comprises a first input (E1) and a first output (S1) which are capable respectively of receiving and delivering a plurality of analog signals and corresponding digital signals having different predetermined types of transmission specifications and associated with substantially homothetic predetermined elementary frequency attenuation templates. A second input (E2) and a second output (S2) are also provided, capable respectively of receiving and delivering a plurality of digital signals and corresponding analog signals having different predetermined types of transmission specifications, associated with different, substantially homothetic predetermined elementary frequency attenuation templates, as well as first and second signal conversion means arranged respectively between the first input and output and between the second input and output and including a single digital filter (6) in common, having a single frequency attenuation template which is compatible with all the elementary templates.

Signal processing device using several different filterings, especially

A multiplier for least significant bit first multiplication of a multiplicand coded on n bits by a multiplier coefficient includes a processor which, for each bit of the decimal part of the multiplier coefficient between the least significant bit and the most significant bit, calculates the sum of rank n+1 obtained from partial products of the bit in question with the n bits of the multiplicand and from corresponding sums calculated for the preceding bit or bits of the multiplier coefficient. This prevents internal overflow of the multiplier.

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Grenoble, France

Freddy Balestro