Imagination Technologies Limited

Freddie Rupert Exall

Theo Alan Drane

Joe Buckingham

Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Trailing or leading digit anticipator

A trailing/leading zero counter is described which comprises a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block comprises two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also comprise one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

Trailing or leading zero counter having parallel and combinational logic

A trailing/leading zero counter includes a plurality of hardware logic blocks, each of which calculates one bit of the output value (i.e. the number of trailing/leading zeros depending on whether it is a trailing/leading zero counter). Each hardware logic block includes two blocks of section hardware logic which each receive a section of an input string and generate one or two outputs from this section of bits. Combining logic then combines the outputs of the section hardware logic to generate the bit of the output value. For hardware logic blocks which calculate bits other than the least significant bit of the output, the hardware logic blocks also include one or more OR reduction stages which reduces the length of the input string by pairwise combining of bits using OR gates before the resultant string is divided into two sections and input to the section hardware logic.

A method and apparatus are provided for use in synthesis of RTL integrated circuit design to determine the functional equivalence of designs. For example, the receiver receives a plurality of designs for synthesis in RTL and a data flow graph is derived for each design. Internal bit widths in the data flow graph representations are restricted () to provide a first modified version of each of the designs. These first modified versions are compared each with the design from which it was derived in a comparison unit (). The input bit widths of the data flow graph representation are then restricted to be no wider than the output bit widths () to derive second modified versions of the designs (). These second modified versions are compared with each other () to determine which are equivalent. Equivalent designs can be passed to an RTL synthesis unit, or otherwise further evaluated.

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Watford, United Kingdom

Freddie Rupert Exall