International Business Machines Corporation

Fred T Tong

Richard Edward Matick

Chiao-Mei Chuang

Peter James Osler

A system providing a guess mechanism for improving the speed of translating effective addresses produced by a processor to real addresses in memory is disclosed wherein a set of Lookaside Tables and logic elements are used along with a set of validity registers and an MRU register to guess at the appropriate real frame index from one of the Tables to be output in the real address in the first cycle of a two cycle operation. The low order bits of the effective address are sent to index the Tables during the first cycle and the high order bits are used during the second cycle for comparison with the set of Table entries selected in the first cycle as containing the real frame index that is output. The selection of the actual real frame index that is output involves a guess using the validity and MRU registers along with indexing of the Tables by a portion of the low order bits. If the logic indicates, upon comparison of 1) the Table entry containing the real frame index that is output during the first cycle with 2) the high order bit comparison of the second cycle, that the selected real frame index was inappropriate, a signal is sent after the second cycle to invalidate the output of the real address incorporating that real frame index.

Guess mechanism for virtual address translation

An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write CPU access function which provides an architectural organization for allowing the chip to be used in (1) a fast, 'late-select' operation which may be provided with any desired degree of set-associativity while achieving an effective one-cycle write operation, and (2) a cache reload function which provides a highly parallel store-back and reload operation to substantially reduce the reload time, particularly for a store-in cache organization. The cache chip organization and architecture provide a late-select cache having a nearly transparent, multiple word reload by incorporating a Cache-Reload Buffer, a store-back buffer and a load-through function all included on the cache array chip for reloading, and a delayed write-enable for achieving an effective one-cycle write operation. Two separate decoder functions are integrated on the chip, one for cache access for normal read/write operations to and from the CPU and one for cache reload which also provides interim access to data which has been transferred out of main memory to the chip but not yet reloaded into the cache array. These two decoders provide for different accessing modes as required of the CPU or main memory operations.

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Hopewell Junction, NY, United States of America

Fred T Tong