Via Technologies, Inc.

Fred Liao

Yijung Su

Mark Zheng

Yiping Chen

John Wakefield Brothers

Michael Hong

Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.

Systems and methods for managing texture descriptors in a shared texture engine

Provided are methods for managing texture data in Graphics Processing Units (GPUs). The methods include receiving, into an arbiter, a preload request configured to request processing of texture data in advance of shader processing and receiving, into the arbiter, a dependent read request configured to request processing of texture data after shader processing. The methods also include receiving, into the arbiter, a capacity signal from a texture buffer and determining, utilizing the virtual buffer capacity signal, a selected request corresponding which of the preload request and the dependent read request is granted. The methods further include processing, in a texture processor, texture data corresponding to the selected request.

Systems and methods for managing texture data in a computer

Systems and method for providing shared attribute evaluation circuits in a graphics processing unit are provided. One embodiment can be described as a system for evaluating attributes in a graphics processing unit having a plurality of processing stages. The system can include an evaluation block, configured to process a plurality of attributes corresponding to a plurality of pixels and a plurality of FIFO buffers, each configured between one of the plurality of processing stages and the evaluation block. An embodiment can further include a shared buffer, configured to store the plurality of attributes or pointers during the attribute processing and processing priority logic, configured to determine a plurality of priorities corresponding to the plurality of attributes.

Systems and methods for providing shared attribute evaluation circuits in a graphics processing unit

Z buffer traffic experienced during graphics processing is reduced by using a compression mechanism to reduce the amount of information stored in the z buffer. The compression mechanism may be a delta-based z compression mechanism, which stores deltas in the z buffer rather than actual z values. These deltas may be used at a later time to compute the z values. By storing deltas instead of actual z values, the compression mechanism makes it possible to store significantly less information in the z buffer. By reducing the amount of information stored in the z buffer, less information will be read from and written to the z buffer, which in turn, reduces z buffer traffic. To further reduce z buffer traffic, selected deltas may be stored not in the z buffer but rather in a storage local to a graphics processing mechanism (GPM). Storing selected deltas in local storage obviates the need to read from or write to the z buffer for those deltas. As a result, z buffer traffic is even further reduced.

Mechanism for reducing Z buffer traffic in three-dimensional graphics processing

Systems and methods are provided for compressing computer graphics color data in a system utilizing a multi-sample anti-aliasing scheme using multiple planes for storing color data samples. Each of the planes is configured as a block of contiguous memory.

Growing community of inventors

San Jose, CA, United States of America

Fred Liao