Fujitsu Corporation

Amdahl Corporation

Fred K Buelow

John J Zasio

Laurence H Cooke

Robert J Beall

A large scale integrated circuit with external integral access test circuitry having a semiconductor body with a surface. A large scale integrated circuit is formed in the semiconductor body through the surface and comprises a large number of interconnected circuit elements with a large number of input and output pads connected to the circuit elements and disposed near the outer perimeter of the semiconductor body. An integrated test circuit is formed in the semiconductor body and extends through the surface. The integrated test circuit has a plurality of probe pads carried by the semiconductor body and connected to the test circuit. The integrated test circuit is formed external of but in relatively close proximity to the large scale integrated circuit. Leads are provided on the semiconductor body which connect the integrated test circuit to the large scale integrated circuit whereby access can be obtained to the large scale integrated circuit through probing of the probe pads of the integrated test circuit to ascertain the characteristics of the large scale integrated circuit.

Large-scale integrated circuit with integral bi-directional test circuit

An electron beam exposure system and method for use in the process of fabricating microminiature devices at high speeds. The high-speed operation is achieved with a computer providing programmed commands specifying a particular pattern to be scanned. A processor, responsive to programmed data, generates scan data a line at a time and loads a line generator. The line generator steps to each exposure location in a line to provide control signals for controlling the position of the electron beam. The starting and end positions of scan lines in both the X and Y directions may be arbitrarily selected thereby eliminating the need for scanning areas not intended to be processed.

Electron beam exposure system method and apparatus

An electron beam exposure apparatus and method for use in fabricating semiconductor devices. A chip pattern larger in area than the electron beam scan field is divided into and exposed in a number of smaller parts (called partitions). The work piece on which the chip pattern is to be formed is moved relative to the scan field to enable each partition to be individually scanned at a different work piece position. The scan field, with the work piece positioned to scan one partition, overlaps onto and establishes a boundary region on an adjacent partition. Portions of chip patterns which lie in a boundary region are selectively scanned in connection with one or another of the abutting partitions. Portions of chip patterns falling in the boundary regions are selected for scanning in one or the other of adjacent partitions so as to minimize the number of divisions and so as to avoid dividing the pattern along critical dimensions.

Overlapping boundary electron exposure system method and apparatus

A high density multilayer printed circuit card assembly having plated through holes in electrical contact with the layers of conducting metal. The card is provided with bonding pads in contact with the plated through holes whereby wiring may be selectively utilized to form interconnections for components carried by the card. Signal lines are brought to the surface so that they can be interrupted and changes be made by wiring. Components of various types are arranged in rows to facilitate cooling.

High density multilayer printed circuit card assembly and method

LSI chip construction having a semiconductor body with a plurality of transistors formed in the semiconductor body in a predetermined pattern and a plurality of resistors formed in a semiconductor body in a predetermined pattern. Means is provided which includes two layers of metallization having input and output pads adjacent the outer perimeter of the body and contacting said transistors and resistors to form a plurality of emitter-follower circuits with certain of the emitter-follower circuits being made up of larger transistors and being located near the perimeter of the chip and near the input-output pads. The other emitter coupled circuits are clustered in groups to form an array of such groups with each of the groups being capable of containing a plurality of logic circuits.

Growing community of inventors

Los Altos Hills, CA, United States of America

Fred K Buelow