International Business Machines Corporation

Fred John Towler

Reid A Wistort

Robert E Busch

Kevin A Batson

Harold Pilo

George Maria Braceras

Robert C Wong

Jason Edward Rotella

Gary S Koch

Chad Allen Adams

Garrett Stephen Koch

Robert Dean Adams

Steven Harley Lamphier

Michael J Schneiderwind

An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configured to introduce a voltage lower than a nominal logic low supply voltage onto the common discharge node following the discharge of the common discharge node, write data lines and bit lines; and a clamping device coupled to the common discharge node, the clamping device configured to limit the magnitude of negative voltage applied to common discharge node by the negative boost circuitry so as to prevent activation of non-selected bit switches.

Apparatus and method for implementing write assist for static random access memory arrays

A design structure comprising an apparatus which reduces the power in memory devices in general and, in particular, static random access memory (SRAM) arrays featuring sense amplifier assist (SAA) circuitry. The design structure limits the implementation of the SAA circuitry to SRAM array blocks that do not meet the application voltage requirements.

Sense-amplifier assist (SAA) with power-reduction technique

An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.

Memory device with data line steering and bitline redundancy

A Content Addressable Memory (CAM) cell with PFET passgate SRAM cells which results in a smaller cell size because of the more balanced number of 8 PFET devices and 8 NFET devices. The PFET passgates allow the size of the SRAM cell pulldown devices to be reduced, and lower the power dissipation in the SRAM during standby or during read/write.

Content addressable memory with PFET passgate SRAM cells

The present invention provides a memory architecture that allows memory checking and replacement of defective words by spare elements already provided on the chip that do not increase the chip size. The method of the invention uses a separate redundant array architecture to provide address translation, so that the redundant entries are represented as the correct entry index that they are replacing.

Redundant array architecture for word replacement in CAM

A match line circuit in a content addressable memory (CAM) has a match line coupled to a first pull-up device and a first pull-down device at a match node. The first pull-up device has selectively adjustable pull-up impedances associated with it. The match line circuit also includes a second pull-up device coupled to a second pull-down device at a float node, and an enabling signal for activating the match line circuit during a memory comparison operation. The enabling signal precharges the match node to a logic low level and the float node to a logic high level in between memory comparison operations.

Content addressable memory (CAM) having a match line circuit with selectively adjustable pull-up impedances

A method for determining a desired operating impedance for a computer memory circuit includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.

Method and apparatus for adjusting control circuit pull-up margin for content addressable memory (CAM)

A method for determining the memory cell stability of individual memory cells included within a memory array is disclosed. In an exemplary embodiment, the method includes presetting each memory cell to a first logic state and then applying a gradually increasing, controlled leakage current to a node within each memory cell. The voltage of each of the nodes within each corresponding memory cell is then monitored. Then, for each memory cell within the memory array, the level of leakage current which causes the memory cell to be changed from the first logic state to a second logic state is determined. The level of leakage current which causes the memory cell to be changed from the first logic state to the second logic state corresponds to the threshold voltage of a pull-up PFET within the memory cell.

Method and apparatus for identifying SRAM cells having weak pull-up PFETs

A Match-Detection Circuit and Match-Detection method, for low-power-consuming searches in a Content Addressable Memory. A HIT is output when the Match Line rises from a Low voltage level to a higher Match Detection Voltage. The Match Detection Voltage is approximately the conducting threshold voltage of an N-channel Field Effect Transistor (FET), and is normally less than One Half of the Power Supply Voltage. Circuits and methods to turn of the through-current in each MISS-ing entry by a carefully timed control signal at the end of a brief Match Detection Period, are disclosed.

Low power CAM match line circuit

Scannable fuse latches are provided that can override current fuse values, read current fuse values, and latch current fuse values. Using the scannable fuse latches of the current invention allows current fuse values to be overridden, which can be important in testing and failure analysis to place the integrated circuit in a known state. The scannable fuse latches of the current invention also allow current fuse values to be read. This aids failure analysis because the current state of the failed integrated circuit can be determined. Finally, the scannable fuse latches of the present invention allow the current state of fuses to be latched and provided to a core of an integrated circuit.

Scannable fuse latches

A method of testing a first memory such as a RAM having data storage at a plurality of individually addressable storage locations is provided. A portion of the address for the addressable locations of the first memory is supplied as an output from a second memory such as a CAM. The second memory includes a decoder to provide a decoded address as input signals to the second memory. During the testing, first memory specific addresses are provided to the decoder as input. These first memory specific addresses are decoded by the decoder and are gated as input signals to address the first memory. In this way, the decoder which in normal operation provides decoded input signals to the CAM is used to provide input signals to the RAM, thus obviating the need for any scan chain latches surrounding the RAM. This enables conventional testing apparatus to provide the necessary test protocol for the RAM through the decoder normally used by the CAM.

Testing associative memory

An output driver circuit is disclosed that generates an accurate and predictable output impedance driver value corresponding to a programmable external impedance. The output driver circuit includes an external resistance device, voltage comparator device, control logic, an evaluate circuit and off-chip driver (OCD) circuit. Voltage from the external resistance device (VZQ) is compared with voltage created from the evaluate circuit (VEVAL) by the voltage comparator device, which indicates to the control logic whether VEVAL is greater than or less than VZQ. The control logic will adjust the evaluate circuit accordingly with a count until the two voltages are basically equal (i.e., the count is alternating between two adjacent binary count values). At which time the control logic operates the OCD with the lower of the two adjacent count values to produce a proper and predictable driving impedance.

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Essex Junction, VT, United States of America

Fred John Towler