Micron Technology Incorporated

Applied Materials, Inc.

Micro Technology, Inc.

Fred D Fishburn

Luan C Tran

Dinesh Chopra

Hongmei Wang

Martin Ceredig Roberts

Rongsheng Yang

Terrence B McDaniel

Brett W Busch

Kurt D Beigel

Nishant Sinha

Richard H Lane

Sony Varghese

John M Drynan

Forest Chen

Sanh D Tang

Zhiping Yin

Ardavan Niroomand

Richard D Holscher

Eden M Zielinski

Sandra Tagg

James Rominger

Howard E Rhodes

Vishnu Kumar Agarwal

Ulrich C Boettiger

Jeffrey A McKee

Tomohiko Kitajima

Gill Yong Lee

Sung-Kwan Kang

Chang Seok Kang

Yoshiki Hishiro

Scott A Southwick

Venkateshwaran Vaiyapuri

Er-Xuan Ping

John K Lee

Casey R Kurth

Kevin R Shea

Janos Fucsko

Lyle D Breiner

Robert J Hanson

Shenlin Chen

Brent A McClure

James L Dale

Troy V Gugel

T Earl Allen

Debra K Gould

Randall Culver

A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.

L-type wordline connection structure for three-dimensional memory

A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

Three dimensional memory device and method of fabrication

Disclosed are 3-D DRAM devices and methods of forming 3-D DRAM devices. One method may include forming a stack of DRAM device layers, forming a MOS substrate directly atop the stack of alternating DRAM device layers, and forming a trench through the MOS substrate and the stack of DRAM device layers. The method may further include depositing a protection layer over the MOS substrate, wherein the protection layer is deposited at a non-zero angle of inclination relative to a vertical extending from a top surface of the MOS substrate.

CMOS over array of 3-D DRAM device

A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed.

Memory arrays

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

Apparatuses, multi-chip modules and capacitive chips

Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region.

Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accesssing and forming the same

Methods for forming memory devices and integrated circuitry, for example, DRAM (dynamic random access memory) circuitry, structures and devices resulting from such methods, and systems that incorporate the devices are provided.

Methods of forming conductive contacts

Multi-semiconductor material vertical memory strings, strings of memory cells having individually biasable channel regions, memory arrays incorporating such strings, and methods of accessing and forming the same

Growing community of inventors

Manassas, VA, United States of America

Fred D Fishburn