Cypress Semiconductor Corporation

Fred B Jenne

Loren T Lancaster

Krishnaswamy Ramkumar

Manuj Rathor

Raymond E Bloker

Rituparna Shrivastava

A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step ), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step ), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step ).

Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices

A semiconductor device and method of manufacturing a semiconductor device is disclosed in which a SONOS-type dielectric may include a charge storing dielectric (206) that includes at least one charge trapping dielectric layer (212) formed within. A charge trapping dielectric layer (212) may be a silicon-rich silicon nitride layer that may trap charge that could otherwise tunnel through a charge storing dielectric (206). A method may include forming a tunneling dielectric (302), forming a first portion of a charge storing layer (304-0), forming a charge trapping layer (306), forming a second portion of a charge storing layer (304-1), and forming a top dielectric (308).

Semiconductor device having silicon-rich layer and method of manufacturing such a device

According to one embodiment, a nonvolatile storage circuit (,) can include a volatile portion (,) that includes p-channel metal-oxide-semiconductor (MOS) transistors (,-,and,-,) and n-channel MOS (NMOS) transistors (,-,and,-,) arranged in a complementary MOS (CMOS) latch configuration. Also included are nonvolatile devices (,-,and,-,) disposed between PMOS transistor,-,and NMOS transistor,-,, and between PMOS transistor,-,and NMOS transistor,-,. Nonvolatile devices (,-,and,-,) can include silicon-oxide-nitride-semiconductor (SONOS) transistors that can be programmed to opposite states to recall a logic value when power is applied to the nonvolatile storage circuit (,). In a read mode, a bias voltage VBIAS can be applied to nonvolatile devices (,-,and,-,) that tends to retain charge in both nonvolatile devices (,-,and,-,).

Silicon-oxide-nitride-oxide-semiconductor (SONOS) type memory cell and method for retaining data in the same

A CMOS semiconductor device which avoids latchup in the powerup mode as well as in the normal operating mode is provided. The device is provided with an on-chip back bias generator which greatly reduces the possibility of forward biasing parasitic NPNP transistors in normal operation. During the powerup mode, before the backbias voltage becomes effective, a clamp diode provided in integrated form outside a guardring surrounding the circuit elements is effective to clamp a large negative voltage that may be created by a 'hot-socket' connection to an output. In a modified form of the invention, a junction field effect transistor is provided to prevent forward biasing of the parasitic transistors in a somewhat different manner.

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Los Gatos, CA, United States of America

Fred B Jenne