Stmicroelectronics S.a.

Stmicroelectronics Gmbh

Medtronics, Inc.

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Kalray

François Jacquet

Philippe Roche

David C McClure

Mark A Lysinger

Richard Ferrant

Mehdi Zamanian

Larry Earl Tyler

Paul F Gerrish

Marc Sabut

Kevin K Walsh

Laurent Murillo

Gilles Gasiot

Sébastien Barasinski

Thierry Devoivre

An SRAM having two capacitors connected in series between respective bit storage nodes of each memory cell. The two inverters of the memory cell are powered by a positive voltage and a low voltage. The two capacitors are connected to each other at a common node. A leakage current generator is coupled to the common node. The leakage current generator supplies to the common node a leakage current to maintain a voltage which is approximately halfway between the voltages of the high and low SRAM supplies.

Robust SRAM memory cell capacitor plate voltage generator

A memory device of SRAM type has a memory plan constituted by base memory cells organized in lines and in columns. Each cell of a column is connected between two bit lines which are precharged during a reading operation. Circuitry is provided for generating a precharge voltage of the bit lines which is less than a nominal supply voltage of the device.

Memory device of SRAM type

A memory circuit has a high voltage and low voltage supply nodes. One of a first and second sets of voltages is selectively applied to the supply nodes of the memory circuit in dependence upon memory operational mode. If in active read/write mode, then the first set of voltages is selectively applied. Conversely, if in standby no-read/no-write mode, then the second set of voltages is selectively applied. A low voltage in the second set of voltages is greater than a low voltage in the first set of voltages by a selected one of a plurality of low offset voltages, and a high voltage in the second set of voltages is less than a high voltage in the first set of voltages by a selected one of a plurality of high offset voltages. The offset voltages are provided by diode-based circuits that are selectively active. Selective activation is provided by either selectably blowable fuse elements or selectively activated switching elements.

Programmable SRAM source bias scheme for use with switchable SRAM power supply sets of voltages

A circuit includes a memory cell having a high voltage supply node and a low voltage supply node. Power multiplexing circuitry is included to selectively apply one of a first set of voltages and a second set of voltages to the high and low voltage supply nodes of the cell in dependence upon a current operational mode of the cell. If the cell is in active read or write mode, then the multiplexing circuitry selectively applies the first set of voltages to the high and low voltage supply nodes. Conversely, if the cell is in standby no-read or no-write mode, then the multiplexing circuitry selectively applies the second set of voltages to the high and low voltage supply nodes. The second set of voltages are offset from the first set of voltages. More particularly, a low voltage in the second set of voltages is higher than a low voltage in the first set of voltages, and wherein a high voltage in the second set of voltages is less than a high voltage in the first set of voltages. The cell can be a member of an array of cells, in which case the selective application of voltages applies to the array depending on the active/standby mode of the array. The array can include a block or section within an overall memory device including many blocks or sections, in which case the selective application of voltages applies to individual blocks/sections depending on the active/standby mode of the block/section itself.

SRAM with switchable power supply sets of voltages

A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.

Memory integrated circuit, in particular an SRAM memory integrated circuit, and corresponding fabrication process

A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.

Logic cell protected against random events

A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.

SRAM memory cell protected against current or voltage spikes

An array of ROM cells, each formed of a transistor having a first drain or source region connected to a bit line connecting several transistors in a first direction, the gates of the different transistors being connected to word lines in a second direction perpendicular to the first one, the array comprising a repetition of an elementary pattern extending over three lines in each direction and comprising nine transistors arranged so that each of the lines of the elementary pattern comprises two cells, two neighboring transistors of each pattern in the first direction sharing a same second region connected to a ground line and being connected to different bit lines from a word line to the other.

Read-only memory

A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells, each latch cell comprising a set of redundant data storage nodes. The transfer ports each include circuitry for writing data separately into each storage node.

Multivibrator protected against current or voltage spikes

A content addressable memory (CAM) includes first and second memory circuits and a comparison circuit. The first memory circuit includes first and second sets of transistors for the storage of first and second compare data. The second memory circuit includes first and second sets of transistors for the storage of enabling or disabling data. The comparison circuit includes first and second sets of comparison transistors which respectively provide for the comparison of the first and second compare data with first and second input data under the control of an output signal from the second memory circuit. The transistors of the first and second sets of transistors of the memory circuits each includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistors of the second conductivity type are formed on the same first active zone of the semiconductor substrate. The first and second sets of comparison transistors of the comparison circuit are formed in separate active zones, respectively, which are mutually separated by the first active zone.

CAM cells and CAM matrix made up of a network of such memory cells

A multivibrator includes a first data transfer port that receives, as input, multivibrator input data. A first, master, latch cell is connected on the output side of the first transfer port. A second, slave, latch cell is connected thereto through a second data transfer port placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes for storing information in at least one pair of complementary nodes and circuitry for restoring information in its initial state, after a current or voltage spike has modified the information in one of the nodes of the said pair, on the basis of the information stored in the other node. The nodes of each pair are implanted opposite one another in a zone of a substrate defining the latch cell.

Implementation of a multivibrator protected against current or voltage spikes

An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

Memory circuit with shared redundancy

A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

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Froges, France

François Jacquet