Deutsche Itt Industries Gmbh

Micronas Gmbh

Trident Microsystems (far East) Ltd.

Micronas Intermetall Gmbh

Abb Ag

Abb Schweiz Ag

Franz-Otto Witte

Miodrag Termerinac

Christian Bock

Miodrag Temerinac

Andreas Menkhoff

Carsten Noeske

Martin Winterer

Frank Brenk

Wolfram Strepp

Florian Zowislok

Markus Klumpp

Exemplary methods are directed to insulation monitoring of non-grounded electrical DC power supply systems and AC power supply systems which have a resistive (R) and capacitive (C) insulation impedance between the power supply system and ground. The method includes applying a pulsed AC voltage (U) having alternately different pulsed voltage values to the power supply system to be monitored via a resistive system interface (R) between the power supply system and ground. The insulation impedance (R) between the power supply system and ground is determined using time profiles of transient processes of the measurement voltage (V) prior to transient recovery of the power supply system to the respective pulsed voltage value (U) of two polarity-inverted pulsed voltage value application processes.

Method and device for insulation monitoring of non-grounded electrical DC and AC grids

The invention relates to a method and a circuit for carrier control in a quadrature demodulator, wherein a complex-value input signal (I, Q) is supplied to a mixer () to perform mixing with a mixing frequency (fm) to create a mixed signal (Ir, Qr), the mixed signal (Ir, Qr) is supplied to a processing section (s) to generate a processed signal (Ie, Qe), the processed signal (Ie, Qe) is supplied to phase measurement device () in order to measure a phase (&#x3c6;m) of the processed signal (Ie, Qe) and the measured phase (&#x3c6;m) is supplied to a phase controller () in order to control the mixing frequency (fm); wherein an idle time (z) is created at least during the processing in the processing section (). To enable a fast switching-on transition, the mixing frequency (fm) is summed or integrated to create a mixing phase (&#x3c6;c), the mixing phase (&#x3c6;c) is used for the mixing operation, as well as fed back to the phase control (), and an error created by the feedback is compensated for with a time-delayed second feedback of the mixing phase (&#x3c6;c).

Method and circuit for carrier control in a quadrature demodulator

The invention relates to a method for determining the sampling instant of a clock signal (t) for a circuit for determining symbols (Se) from a digitized signal (sd, S) which is coupled to at least one quadrature signal pair of a modulation method (QAM), wherein the digitized signal is converted to polar signal coordinates (R, &#x3b1;) with a radial component (R).

Method and circuit for determining a clock signal sampling instant for symbols of a modulation method

A DC voltage transformer includes an oscillator, which can be controlled in terms of a characteristic such as its phase and/or frequency, and a modulation circuit that provides a periodic or random control signal to the oscillator. A power switch is connected in series with an inductance between two power supply potentials, the power switch being switched between open and closed states. A first smoothing capacitor is connected directly between the two power supply potentials, and a second smoothing capacitor is arranged in series with a Zener diode, with both the capacitor and diode being connected in parallel with the main terminals of the power switch. A modulated reference signal form the oscillator is connected to the control input of the power switch. The modulation of the reference signal can be of any type, for example a periodic modulation that is a periodic variation of the phase and/or the period of the reference signal made possible by for example a sine wave. The pulse duty factor of the reference signal is used to establish the relation between an input voltage and an output voltage of the transformer.

Direct current voltage transformer

The invention relates to a method for encrypting or decrypting a sequence of successive data words in a data communications device, the method comprising executing an algorithm in which a sequence of quasi-random encryption words is generated from predetermined start values by performing operations in a finite group, and in which a respective one of the encryption words is combined with a respective one of the data words.

Method for encryption or decryption using finite group operations

A carrier control loop (,) for a receiver of digitally transmitted signals is disclosed comprising, in the direction of signal flow, a quadrature demodulator (,), a symbol recognition device (,), a detector (,) for forming a phase deviation value (&phgr;d) and/or a frequency deviation value (fd), a feedback device (,), and a variable-frequency oscillator (,) connected to the quadrature demodulator (,). An evaluating device (,) determines from signals (I, Q) of the carrier control loop (,) a reliability value (z) for the measured phase deviation value (&phgr;d) and/or frequency deviation value (fd), and controls the carrier control loop (,) in accordance with the determined reliability value.

Carrier control loop for a receiver of digitally transmitted signals

An asymmetric filter combination (F1, F2) for the transmission of a binary data stream (st) between a transmitter (T) and a receiver (R) is disclosed which includes a first filter (F1) at the transmitter end having an FIR structure and a second filter (F2) at the receiver end having an IIR structure, with the combination of the first and second filters (F1, F2) yielding a common transfer function which satisfies both the Nyquist criterion and the noise-matching criterion.

Asymmetric filter combination for a digital transmission system

A transmission system and a transmitter (T) for such a system are disclosed for transmitting a digital signal (sr), encoded in symbols (Si), from the transmitter (T) to a receiver (R) at an arbitrary frequency position by quadrature modulation. In the transmitter, one of the two quadrature components (ki, kq) is delayed before the quadrature modulation by a given time interval (td).

Transmission system in which either an in-phase or quadrature component

Transmission system with a transmitter (T), a receiver (R), and a filter combination (FI1, FI2; FQ1, FQ2) for transmitting a digital signal (sr), encoded in symbols (Si), from the transmitter (T) to the receiver (R) at any frequency position by quadrature modulation, wherein one of the two quadrature signal components (ki, kq) in the transmitter is delayed before the quadrature modulation by a time interval td, particularly by td=Tsymb/4. (FIG. 7)

Transmission system for digital signals, and transmitter and receiver

A multiplier for real or complex numbers is split at each data input into two equally large digit ranges to determine partial products in separate subfields. Within a rectangular partial-product field, the subfields are rearranged according to the real or complex arithmetic operation to be performed, the rearrangement being effected by assigning basic weights to the individual subfields. By means of an adding arrangement, the partial products of the individuals subfields are added in a positionally correct manner to form the digits of a real or complex output number.

Multiplier apparatus and method for real or complex numbers

Digital demodulator for a quadrature-modulated signal (sq) which transmits a combination signal by amplitude and phase modulation. A quadrature-signal source provides a digitized in-phase component (I) and a digitized quadrature component (Q) of low frequency. A resolver converts the two components (I,Q) into a magnitude signal (b) and a first phase signal (p1). A first feedback control loop and a second feedback control loop that maintains the slope (mp) of the first phase signal (p1) at the zero value and the time average (pm1) at the zero phase position, whereby a third phase signal (p3) is formed. From the resulting signals (b, p3, p3') a decoder forms at least one of the required components (R,L,P).

Digital demodulator for quadrature amplitude and phase modulated signals

A complementary clock system is disclosed for producing antiphase clock signals. The system includes a clock generator for producing a first clock signal (t3) and a second clock signal (t4). A first and second driver stage coupled to the clock generator for driving respective clock lines having a capacitive load that corresponds to a first load capacitance and a second load capacitance, respectively. A switchable current path coupled between the first and second clock lines which contains a gating circuit and at least one inductive element. The gating circuit being in a conducting state essentially during the switching intervals (ti) of the first and second clock signals (t3, t4).

Complementary clock systems

An improved method for digital interpolation of signals for a second interpolation filter is disclosed which permits a high signal/noise ratio with a minimum amount of circuitry for an overall system comprising first and second interpolation filters. The method for digital interpolation of signals requires multiplying delayed input values locked to a first signal by corresponding weighting factors which are dependent on a time-difference value determined by the interpolating instant and the time grid of the first clock signal. The weighting factors are determined by an impulse response in the time domain. The associated transfer function has an attenuation characteristic in the frequency domain which, with respect to the stop bands, is limited essentially to the alias regions located at the frequency multiples of the first clock signal. Each of these alias regions is assigned at least two adjacent zeros, or in the presence of double-order zeros, at least one of the alias regions and the associated periodic alias regions are assigned at least one further zero of the transfer function.

Method for digital interpolation

An apparatus and method increase the data-processing speed of a signal processor whose signal-processing unit includes at least one arithmetic logic unit and one multiplier which are fed with input data of n-bit word length. When such a signal processor is supplied from a source with input-data words having a shorter word length than the maximum word length of n bits of the signal processor, invalid bits are masked during the loading process. The loading operation is accelerated by changing the contents of the input-data words using a mask value in at least one presettable masking unit before the input-data word is processed by the signal-processing unit.

Growing community of inventors

Emmendingen, Germany

Franz-Otto Witte