Ocz Technology Group, Inc.

Ocz Storage Solutions Inc.

Sanmina Corporation

Bcinet, Inc.

Other

Toshiba Corporation

4d-s, Ltd.

Datasecure LLC

Olantra Fund X L.l.c.

Brain Actuated Technologies

Oc2 Technology Group, Inc.

Cui Global, Inc.

Franz Michael Schuette

Ryan Maurice Petersen

Yaron Klein

Anthony Leach

Charles C Hill

Ritesh Kumar

Lutz Filor

William J Allen

Gary James Calder

Stephen Jeffrey Smith

Matthew T Bowman

William Ward Clawson

Lee Edward Cleveland

Drew George Doblar

G R Mohan Rao

Kais Belgaied

Matthew Phillip Mitchell

Andrew Junker

Allon Leon Cohen

Eugene McCabe

Eric L Nelson

Lawrence Allan Freymuth

Hyun Mo Chung

Paul Batcheller

Richard Elling

Daniel M Gale

Donald Chong Lee

Bhulinder Sethi

One feature pertains to a modular design of a motherboard for a computer system. The mother board is disaggregated into a CPU board and an IO board. The CPU board contains at least one CPU, the associated memory subsystem and the voltage regulator module. The integrated IO ports escape to a high speed connector mating with its counterpart on an IO board which contains all peripheral devices including system logic not part of the CPU. In a multi-socket configuration the CPUs are on the CPU board and the processor interconnects are routed directly in a point to point manner.

Modular motherboard for a computer system and method thereof

A server computer is configured to write a first copy of a block of data to a first namespace on a first non-volatile memory-based cache drive and a second copy of the block of data to a RAID controller for de-staging of the data to hard disk drives of a RAID array. Acknowledgment of hardening of the data on the hard disk drives initiates purging of the first copy of the block of data from the cache drive. High availability is enabled by writing a third copy of the block of data to a second server to store the block of data in a second namespace on a second non-volatile memory-based cache drive. Restoring of data after power loss accesses the data on the first non-volatile memory-based cache drive.

Method and apparatus for consistent and highly available data storage using local and fabric attached non-volatile memory storage devices

A network-attached storage device is provided comprising a network card with an embedded operating system that provides autonomous operation of the network card, the network card including a network port to communicate with an external device and a peripheral component interconnect express (PCIe) interface to couple to a first PCIe device in the absence of a system host processor.

Modular non-volatile memory express storage appliance and method therefor

A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media.

Delay circuitry to hold up power to a mass storage device and method therefor

One feature pertains to a scissor-based carrier assembly for a mass storage device used in a storage computer system. The carrier assembly has fixed and moving parts allowing the carrier to change from a retracted state to insert or remove the mass storage device into or from a storage enclosure to an extended state to couple the mass storage device with a connector of the storage computer system.

Drive carrier and method therefor

One feature pertains to cooling of a high density array of non-volatile memory mass storage devices within a computer enclosure. A coolant is moved through the enclosure through two separate air paths, each serving approximately half of the mass storage devices. The two air paths are interleaved in a central duct ported to a frontal and a rear plenum. The central duct contains two groups of fans with a flow axis perpendicular to the plane of the server enclosure but with opposite flow direction with the two groups vertically offset relative to each other. The two paths are separated from each other through dividers. Both paths intake coolant from the cold isle and exhaust the coolant to the hot isle. The non-volatile memory mass storage devices include electromechanical and solid state devices.

Apparatuses and methods for cooling high density arrays of non-volatile memory mass storage devices

One feature pertains to an advanced computer device configured for storing data on a plurality of non-volatile memory mass storage devices. The mass storage devices may interface with the computer device through a plurality of base boards mounted in an enclosure that are configured to couple with at least one non-volatile memory storage drive. Each base board may further be configured to couple with a high speed interconnect cable to exchange data to be loaded or stored with the computer device. According to one aspect, the high speed cable transfers Serially Attached SCSI (SAS) or PCIe data packets or frames.

Base board architecture for a server computer and method therefor

A solid-state mass storage device adapted to be used as a cache for an hard disk drive that utilizes a more efficient logical data management method relative to conventional systems. The storage device includes a circuit board, a memory controller, at least one non-volatile memory device, and at least two data interfaces. The storage device is coupled to a host computer system and configured to operate as a cache for at least one hard disk drive. The storage device is interposed between the host computer system and the at least one hard disk drive. Both the storage device and the at least one hard disk drive are coupled to the host computer system through a single connection and configured to operate in a daisy chain configuration.

Cache device for hard disk drives and methods of operations

Methods of operating a non-volatile solid state memory-based mass storage device having at least one non-volatile memory component. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Methods for writing data to non-volatile memory-based mass storage devices

A solid state drive having at least one NAND flash memory component organized in blocks, pages and cells. Each cell is adapted to store at least two bits. Each block of the memory component is adapted to be dynamically configured to store at least one bit per cell using a first mode of operation and dynamically configured to store at least two bits per cell using a second mode of operation while the mass storage device is operating, wherein the first mode of operation entails programming fewer bits of a cell in fewer passes as compared to the second mode of operation.

NAND flash-based storage device and methods of using

RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of '1' to the parity value.

Raid storage systems having arrays of solid-state drives and methods of operation

A host server computer system that includes a hypervisor within a virtual space architecture running at least one virtualization, acceleration and management server and at least one virtual machine, at least one virtual disk that is read from and written to by the virtual machine, a cache agent residing in the virtual machine, wherein the cache agent intercepts read or write commands made by the virtual machine to the virtual disk, and a solid state drive. The solid state drive includes a non-volatile memory storage device, a cache device and a memory device driver providing a cache primitives application programming interface to the cache agent and a control interface to the virtualization, acceleration and management server.

Methods and apparatus for providing acceleration of virtual machines in virtual environments

A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter.

Apparatus, methods and architecture to increase write performance and endurance of non-volatile solid state memory components

A resistive random access memory integrated circuit for use as a mass storage media and adapted for bulk erase by substantially simultaneously switching all memory cells to one of at least two possible resistive states. Bulk switching is accomplished by biasing all bottom electrodes within an erase area to a voltage lower than that of the top electrodes, wherein the erase area can comprise the entire memory array of the integrated circuit or else a partial array. Alternatively the erase area may be a single row and, upon receiving the erase command, the row address is advanced automatically and the erase step is repeated until the entire array has been erased.

Methods and circuits for bulk erase of resistive memory

A method and mass storage device that combine multiple solid state drives (SSDs) to a single volume. The device includes a carrier board and at least two solid state drives having power and data connections to the carrier board. The carrier board includes a circuit board functionally connected to a control logic and at least two secondary connectors that are disposed at different edges of the circuit board and functionally connected to the control logic. The solid state drives are connected to the carrier board through the secondary connectors, and each solid state drive has a power and data connector directly connected to one of the secondary connectors of the carrier board. The solid state drives are oriented substantially parallel to the carrier board and to each other.

Growing community of inventors

Colorado Springs, CO, United States of America

Franz Michael Schuette