Infineon Technologies Ag

Intel Corporation

Intel Mobile Communications Gmbh

Siemens Aktiengesellschaft

Intel Deutschland Gmbh

Maxlinear, Inc.

Micronas Gmbh

Intel IP Corporation

Franz Kuttner

Michael Fulde

Peter Bogner

Bernd-Ulrich Klepser

Davide Ponton

Dieter Draxelmayr

Daniel Gruber

Markus Schimper

Gerhard Knoblinger

Antonio Passamani

Christian Vogel

Kameran Azadet

Martin Clara

Christian Cornelius Russ

Alexander Belitzer

Christian Mayer

Edwin Thaller

Lukas Doerrer

Peter Preyler

Hundo Shin

Werner Hoellinger

Florian Mrugalla

Michael Kalcher

Jovan Markovic

Alexander Klinkan

Tobias Buckel

Alan Paussa

Damir Hamidovic

Bernhard Stein

Luis Giles

Matej Kus

Navatouch Deeying

Giuseppe Curello

Tomasz Biedrzycki

Luis F Giles

A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50&#x3a9;.

Digital-to-analog converter, transmitter and mobile device

A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20&#x3a9;. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.

Digital-to-analog converter

High efficiency amplitude DACs (Digital-to-Analog Converters) and RFDACs (Radio Frequency DACs) employing such amplitude DACs are discussed. One exemplary embodiment is a DAC comprising a plurality of DAC stages, wherein each DAC stage of the plurality of DAC stages is associated with a respective predetermined voltage of a plurality of predetermined voltages, wherein each DAC stage of the plurality of DAC stages can receive a digital signal at the respective predetermined voltage associated with that DAC stage when the respective predetermined voltage of that DAC stage is a selected predetermined voltage, wherein the selected predetermined voltage is based on an amplitude of the digital signal, and wherein each DAC stage of the plurality of DAC stages can generate a respective analog signal associated with that DAC stage based on the digital signal received at that DAC stage when the respective predetermined voltage of that DAC stage is the selected predetermined voltage.

RFDAC (RF (Radio Frequency) DAC (Digital-to-Analog Converter)) with improved efficiency and output power

Systems, methods, and circuitries enable selected signal components to be isolated in a feedback transmit signal that includes multiple signal components. In one example, a signal component cancellation system for a feedback receiver includes a transmit chain configured to transmit a transmit signal having at least two signal components with offset center frequencies. The system includes measurement circuitry configured to measure a received signal that results from feedback of the transmit signal and cancellation circuitry configured to cancel a selected signal component from the transmit signal to generate a cancellation signal. The system further includes subtraction circuitry configured to combine the cancellation signal with the measured received signal to generate a component signal corresponding to a contribution of the selected signal component to the received signal and provide the component signal to the feedback receiver.

Signal component cancellation for feedback receiver

A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

Signed-RFDAC architectures enabling wideband and efficient 5G transmitters

CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.

CDAC (capacitive DAC (digital-to-analog converter)) unit cell for multiphase RFDAC (radio frequency DAC)

Measurement apparatuses and methods are described. A measurement input is coupled with a first terminal of a capacitance via a first switch, and a reference voltage is coupled with the first terminal of the capacitance via a second switch. A measurement circuit is coupled to a second terminal of said capacitance.

Measurement apparatus

Techniques are disclosed to provide a data dependent delay for a multi-phase transmitter architectures. These techniques include identifying a current segment occupied by a symbol associated with in-phase (I) and quadrature phase (Q) data within a data constellation based upon the number of phases used. Once the segment is identified, vector components are calculated as a function of the segment used to re-map the symbol within the constellation defined in accordance with the number of phases. The data delay may be performed in the baseband or at the RF rate to time-align local oscillator clocks with the delayed data, which is represented as the calculated vector components, for transmission. Further modifications to the RF-DAC operation to facilitate operation with the multi-phase system are also disclosed.

Multiphase transmitter digital front end

A digital-to-analog converter (DAC) linearization system can include a DAC configured to generate an analog output signal based on a digital input signal, a detector configured to detect noise on a supply voltage and generate a noise detection signal based on the detected noise, and a compensator that is configured to generate a compensated analog signal based on the analog output signal and the noise detection signal.

Digital to analog converter linearization system

RFDAC (RF (radio frequency) DAC (digital-to-analog converter)) with improved efficiency and output power

Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

Area-efficient and robust electrostatic discharge circuit

An apparatus is disclosed that includes a transmit chain, a duplexer, a receive chain and a control circuit. The transmit chain is configured to generate a transmit signal at a transmit frequency. The duplexer is configured to pass the transmit signal to an antenna that generates a transmit leakage current into a received signal. The receive chain is configured to obtain the received signal and measure the leakage current from the transmit chain. The control circuit is configured to determine reduced performance parameters for the transmit chain based on the determined leakage signal, wherein the transmit leakage signal is inversely proportional to the reduced performance parameters.

Transmitter performance calibration systems and methods

Disclosed herein is an apparatus and methodology for reducing peak-to-average-power ratio (PAPR) for IQ radio frequency digital-to-analog converter (RFDAC). Processing circuitry may be configured to generate a digital signal comprising an in-phase (I) signal component and a quadrature (Q) signal component having a peak-to-average-power-ratio (PAPR). The processing circuitry may determine the I signal component and the Q signal component are higher than a predetermined threshold value, and limit the I signal component and the Q signal component to be less than or equal to the predetermined threshold value. The processing circuitry may rotate the signal components to generate rotated signal components to reduce the PAPR based on the I and Q signal components having less than or equal to the predetermined threshold value, and may generate an output radio frequency (RF) signal based on the rotated signal components.

PAPR reduction for IQ RFDAC

This disclosure is directed towards techniques and methods of suppressing the effect of modulated clock jitter in a digital to analog conversion (DAC) circuit of a polar modulator in a transceiver. A phase locked loop (PLL) in a modulator circuit may introduce a deterministic jitter in DAC generated pulses which may lead to amplitude variations in the DAC generated pulses. The clock jitter may change the duty cycle of the input amplitude to the DAC which may result in a variation of the output of the DAC generated pulse. A digital pre-distortion or digital multiplier circuit may be introduced before the DAC circuit to increase or decrease the DAC amplitude to compensate for the pulse width modulation.

Digital modulation jitter compensation for polar transmitter

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St. Ulrich, Austria

Franz Kuttner