Infineon Technologies Ag

Qimonda Ag

Sandisk 3d LLC

Rising Silicon, Inc.

Sandisk Technologies Inc.

Infineon Technologies LLC

Erlus Aktiengesellschaft

Franz Kreupl

Deepak Chandra Sekar

Raghuveer S Makala

Martin Gutsche

Robert Seidel

Peter Rabkin

Franz Hofmann

Manfred Engelhardt

Harald Seidl

Ulrich Karl Klostermann

Richard Johannes Luyken

Wolfgang Hönlein

Andrew Graham

Wolfgang Rösner

Jingyan Zhang

Chu-Chen Fu

Johannes Kretz

Georg Duesberg

James K Kai

Thomas Schulz

Michael Specht

Michael Kund

Abhijit Bandyopadhyay

Erhard Landgraf

Huiwen Xu

Klaus-Dieter Ufert

Ulrike Gruening-von Schwerin

Maik Liebau

Petra Majewski

Masaaki Higashitani

Er-Xuan Ping

Thomas Happ

Tuan Duc Pham

Till Schloesser

Bernhard Sell

Harry Hedler

George Samachisa

Jan Boris Philipp

Andrei Mihnea

Mohan Dunga

Wipul Jayasekara

Yung-Tin Chen

Siegfried Schwarzl

Xiying Costa

Till Schl&ouml;sser

Volker Weinrich

Ritu Shrivastava

Ralf Symanczyk

Thomas Peter Haneder

Li Xiao

Eugen Unger

Annette Sänger

Bernhard Ruf

Johannes Luyken

Wolfgang H&ouml;nlein

Sanghyun Lee

Yibo Nian

Dieter Andres

Christian Kapteyn

Hannes Mio

Peter Thieme

Manuela Schiele

Gernot Steinlesberger

Heike Drummer

Werner Simbürger

Hyang-Sook Klose, Legal Representative

Christian Ruester

Rainer Bruchhaus

Ulrike Grüning-von Schwerin

Ulrich Klosterman

Tobias WÄHLER

Rüdiger Grau

Carsten Ackerhans

Alexander Josef Stoll

Alois Hacker

Georg Düsberg

The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Vertical interconnect structure, memory device and associated production method

Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide.

Non-volatile storage with metal oxide switching element and methods for fabricating the same

Trap passivation in memory cell with metal oxide switching element

An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon.

Semiconductor chip with integrated via

In a first aspect, a metal-insulator-metal (MIM) stack is provided that includes (1) a first conductive layer comprising a silicon-germanium (SiGe) alloy; (2) a resistivity-switching layer comprising a metal oxide layer formed above the first conductive layer; and (3) a second conductive layer formed above the resistivity-switching layer. A memory cell may be formed from the MIM stack. Numerous other aspects are provided.

Bottom electrodes for use with metal oxide resistivity switching layers

An integrated circuit includes a memory cell with a resistance changing memory element. The resistance changing memory element includes a first electrode, a second electrode, and a resistivity changing material disposed between the first and second electrodes, where the resistivity changing material is configured to change resistive states in response to application of a voltage or current to the first and second electrodes. In addition, at least one of the first electrode and the second electrode comprises an insulator material including a self-assembled electrically conductive element formed within the insulator material. The self-assembled electrically conductive element formed within the insulator material remains stable throughout the operation of switching the resistivity changing material to different resistive states.

Resistive memory devices with improved resistive changing elements

A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Memory cell with resistance-switching layers

A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.

Structure and fabrication method for resistance-change memory cell in 3-D memory

A circuit is disclosed. The circuit includes at least one nanostructure and a carbon interconnect formed by a substantially carbon layer, wherein the nanostructure and the carbon interconnect are directly coupled to one another.

Electrical circuit with a nanostructure and method for producing a contact connection of a nanostructure

A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.

Carbon/tunneling-barrier/carbon diode

A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Composition of memory cell with resistance-switching layers

Non-volatile storage elements having a P&#x2212;/metal floating gate are disclosed herein. The floating gate may have a P&#x2212; region near the tunnel oxide, and may have a metal region near the control gate. A P&#x2212; region near the tunnel oxide helps provide good data retention. A metal region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also, erasing the non-volatile storage elements may be efficient. In some embodiments, having a P&#x2212; region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.

P-/Metal floating gate non-volatile storage element

A non-volatile resistance-switching memory element includes a resistance-switching element formed from a metal oxide layer having a dopant which is provided at a relatively high concentration such as 10% or greater. Further, the dopant is a cation having a relatively large ionic radius such as 70 picometers or greater, such as Magnesium, Chromium, Calcium, Scandium or Yttrium. A cubic fluorite phase lattice may be formed in the metal oxide even at room temperature so that switching power may be reduced. The memory element may be pillar-shaped, extending between first and second electrodes and being in series with a steering element such as a diode. The metal oxide layer may be deposited at the same time as the dopant. Or, using atomic layer deposition, an oxide of a first metal can be deposited, followed by an oxide of a second metal, followed by annealing to cause intermixing, in repeated cycles.

Resistance-switching memory cell with heavily doped metal oxide layer

In a first aspect, a method of forming a metal-insulator-metal ('MIM') stack is provided, the method including: (1) forming a dielectric material having an opening and a first conductive carbon layer within the opening; (2) forming a spacer in the opening; (3) forming a carbon-based switching material on a sidewall of the spacer; and (4) forming a second conductive carbon layer above the carbon-based switching material. A ratio of a cross sectional area of the opening in the dielectric material to a cross sectional area of the carbon-based switching material on the sidewall of the spacer is at least 5. Numerous other aspects are provided.

Memory cell with carbon switching material having a reduced cross-sectional area and methods for forming the same

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Munich, Germany

Franz Kreupl