Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co. Kg

Other

Franz-Josef Niedernostheide

Hans-Joachim Schulze

Anton Mauder

Christian Philipp Sandow

Frank Dieter Pfirsch

Reiner Barthelmess

Stephan Voss

Maria Cotorogea

Franz Hirler

Roman Baburske

Holger Schulze

Mark-Matthias Bakran

Manfred Pfaffenlehner

Zheming Li

Frank Hille

Daniel Domes

Frank Wolter

Uwe Kellner-Werdehausen

Yvonne Gawlina-Schmidl

Robert Maier

Johannes Georg Laven

Elmar Falck

Hans-Peter Felsl

Thomas Raker

Carsten Schaeffer

Hans Peter Felsl

Armin Willmeroth

Helmut Strack

Joachim Weyers

Markus Schmitt

Stefan Gamerith

Josef Lutz

Björn Fischer

Ralf Siemieniec

Matteo Dainese

Thomas Basler

Christian Jaeger

Alexander Philippou

Vera Van Treek

Carsten Schäffer

Yvonne Gawlina

Francisco Javier Santos Rodriguez

Moriz Jelinek

Antonio Vellei

Jörg Dorn

Markus Bina

Holger Huesken

Thomas Gutt

Holger Ruething

Roman Roth

Frank Umbach

Christian Robert Mueller

Oana Julia Spulber

Wolfgang Wagner

Guang Zeng

Riteshkumar Bhojani

Reinhart Job

Thomas Kuenzig

Judith Specht

Vytla Rajeev Krishna

A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

Power semiconductor device having nanometer-scale structure

A voltage-controlled switching device includes a drain/drift structure formed in a semiconductor portion with a lateral cross-sectional area A, a source/emitter terminal, and an emitter channel region between the drain/drift structure and the source/emitter terminal. A resistive path electrically connects the source/emitter terminal and the emitter channel region. The resistive path has an electrical resistance of at least 0.1 mΩ*cm/A.

Voltage-controlled switching device with resistive path

A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to control a gate voltage to generate an on-current during a plurality of turn-on switching events to turn on the transistor. The gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage, and a second driver configured to, during a boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage. A control circuit measures a transistor parameter representative of a reverse recovery current of the transistor for a turn-on switching event during which the transistor is transitioned to an on state and controls the first driver and controls the second driver based on the measured transistor parameter.

Actively tracking switching speed control and regulating switching speed of a power transistor during turn-on

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

Gate control method of MOS-gated power device

A semiconductor component includes a semiconductor body having opposing first surface and second surfaces, and a side surface surrounding the semiconductor body. The semiconductor component also includes an active region including a first semiconductor region of a first conductivity type, which is electrically contacted via the first surface, and a second semiconductor region of a second conductivity type, which is electrically contacted via the second surface. The semiconductor component further includes an edge termination region arranged in a lateral direction between the first semiconductor region of the active region and the side surface, and includes a first edge termination structure and a second edge termination structure. The second edge termination structure is arranged in the lateral direction between the first edge termination structure and the side surface and extends from the first surface in a vertical direction more deeply into the semiconductor body than the first edge termination structure.

Semiconductor component with edge termination region

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Method for reducing oscillation during turn on of a power transistor by regulating the gate switching speed control of its complementary power transistor

A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.

Semiconductor device having active and inactive semiconductor mesas

A power semiconductor transistor includes: a semiconductor body coupled to a load terminal; a drift region in the semiconductor body and having dopants of a first conductivity type; a first trench extending into the semiconductor body along a vertical direction and including a control electrode electrically insulated from the semiconductor body by an insulator; a second trench extending into the semiconductor body along the vertical direction; a mesa region arranged between the trenches and including a source region electrically connected to the load terminal and a channel region separating the source and drift regions; and a portion of a contiguous plateau region of a second conductivity type arranged in the semiconductor drift region and extending below the trenches and below the channel and source regions, the contiguous plateau region having a plurality of openings aligned below the channel region in a widthwise direction of the channel region.

Power semiconductor device

A power semiconductor device includes a semiconductor body having front and back sides. The semiconductor body includes drift, field stop and emitter adjustment regions each of a first conductivity type. The field stop region is arranged between the drift region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the drift region. The emitter adjustment region is arranged between the field stop region and the backside and has dopants of the first conductivity type at a higher dopant concentration than the field stop region. The semiconductor body has a concentration of interstitial oxygen of at least 1E17 cm. The field stop region includes a region where the dopant concentration is higher than that in the drift region at least by a factor of three. At least 20% of the dopants of the first conductivity type in the region are oxygen-induced thermal donors.

A semiconductor die includes a semiconductor body having first and second active portions. The first active portion includes first source regions. The second active portion includes second source regions. A gate structure extends from a first surface into the semiconductor body and has a longitudinal gate extension along a lateral first direction. A first load pad and the first source regions are electrically connected. A second load pad and the second source regions are electrically connected. A gap laterally separates the first and second load pads. A lateral longitudinal extension of the gap is parallel to the first direction or deviates therefrom by not more than 60 degree. A connection structure electrically connects the first and second load pads. The connection structure is formed in a groove extending from the first surface into the semiconductor body and/or in a wiring layer formed on the first surface.

Semiconductor die, semiconductor device and IGBT module

Power semiconductor device having fully depleted channel regions

A method of manufacturing a device in a semiconductor body includes forming a first field stop zone portion of a first conductivity type and a drift zone of the first conductivity type on the first field stop zone portion. An average doping concentration of the drift zone is smaller than 80% of that of the first field stop zone portion. The semiconductor body is processed at a first surface and thinned by removing material from a second surface. A second field stop zone portion of the first conductivity type is formed by implanting protons at one or more energies through the second surface. A deepest end-of-range peak of the protons is set in the first field stop zone portion at a vertical distance to a transition between the drift zone and first field stop zone portion in a range from 3 &#x3bc;m to 60 &#x3bc;m. The semiconductor body is annealed.

Method of manufacturing a semiconductor device comprising first and second field stop zone portions

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Muenster, Germany

Franz-Josef Niedernostheide