Infineon Technologies Austria Ag

Infineon Technologies Ag

Infineon Technologies Dresden Gmbh & Co. Kg

Infineon Technologies Dresden Gmbh

Other

Infineon Technologies LLC

Infineon Technology Austria Ag

Franz Hirler

Anton Mauder

Hans-Joachim Schulze

Armin Willmeroth

Markus Zundel

Hans Weber

Andreas Peter Meiser

Frank Dieter Pfirsch

Ralf Siemieniec

Walter Rieger

Joachim Weyers

Oliver Blank

Martin Poelzl

Uwe Wahl

Stefan Gamerith

Joachim Krumrey

Rolf Weis

Oliver Haeberlen

Ralf Henninger

Gerald Deboy

Martin Henning Vielemeyer

Maximilian Roesch

Markus Schmitt

Stefan Sedlmaier

Till Schloesser

Wolfgang Werner

Winfried Kaindl

Michael Hutzler

Li Juin Yip

Rudolf Zelsacher

Thorsten Meyer

Peter Irsigler

Daniel Tutuc

Martin Feldtkeller

Franz-Josef Niedernostheide

Helmut Strack

Christian Fachmann

Norbert Krischke

Andreas Riegler

Andreas Voerckel

Carolin Tolksdorf

Manfred Kotek

Thoralf Kautzsch

Wolfgang Klein

David Laforet

Matteo-Alessandro Kutschak

Rudolf Berger

Enrique Vecino Vazquez

Holger Kapels

Johannes Georg Laven

Francisco Javier Santos Rodriguez

Matthias Stecher

Werner Schustereder

Johannes Baumgartl

Roman Knoefler

Michael Rueb

Ulrich Glaser

Wolfgang Jantscher

Hans Peter Felsl

Christian Geissler

Steffen Bieselt

Michael Treu

Uli Hiller

Steffen Thiele

Maria Cotorogea

Peter Nelle

Alessia Scire

Christian Kampen

Wolfgang Scholz

Jenoe Tihanyi

Wolfgang Lehnert

Klemens Pruegl

Gerhard Noebauer

Hermann Gruber

Carsten Schaeffer

Elmar Falck

Cedric Ouvrard

Gabor Mezoesi

Andrew Wood

Roland Rupp

Matteo Dainese

Hans-Joerg Timme

Armin Tilke

Wolfgang Roesner

Christian Jaeger

Alexander Philippou

Henning Feick

Thomas Aichinger

Oliver Häberlen

Daniel Domes

Paul Ganitzer

Hubert Rothleitner

Robert Strenz

Georg Ehrentraut

Thomas Gross

Herbert Schäfer

Daniel Kueck

Dorothea Werber

Otto Wiedenbauer

Uwe Schmalzbauer

A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device. The first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body. The first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body. The second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body. The at least one second device region is spaced apart from the first device region.

Transistor arrangement with a lateral superjunction transistor device

An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device () and a second transistor device (); a first biasing circuit () connected in parallel with a load path of the first transistor device () and comprising a first electronic switch (); a second biasing circuit () connected in parallel with a load path of the second transistor device () and comprising a second electronic switch (); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device () and the second electronic switch () based on the first half-bridge input signal (Sin), and drive the second transistor device () and the first electronic switch () based on the second half-bridge input signal (Sina).

Electronic circuit with a transistor device and a biasing circuit

A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

Power semiconductor device having vertically parallel p-n layers formed in an active region under transistor cells and under a non-depletable extension zone formed in the edge region

A semiconductor device includes a semiconductor body, a vertical transistor arranged in a first device region of the semiconductor body, and a lateral transistor arranged in a second device region of the semiconductor body. The vertical transistor includes a plurality of drift regions of a first doping type and a plurality of compensation regions of a second doping type complementary to the first doping type. The drift regions and the compensation regions are arranged alternately in a lateral direction of the semiconductor body. The second device region includes a well-like structure of the second doping type surrounding a first semiconductor region of the first doping type. The lateral transistor includes device regions arranged in the first semiconductor region.

Half-bridge circuit including integrated level shifter transistor

A silicon carbide device includes a transistor cell with a source region and a gate electrode. The source region is formed in a silicon carbide body and has a first conductivity type. A first low-resistive ohmic path electrically connects the source region and a doped region of a second conductivity type. The doped region and a floating well of the first conductivity type form a pn junction. A first clamp region having the second conductivity type extends into the floating well. A second low-resistive ohmic path electrically connects the first clamp region and the gate electrode.

Silicon carbide device with transistor cell and clamp region

A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.

Method for forming an insulation layer in a semiconductor body and transistor device

Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Electronic circuit having a transistor device and a biasing circuit

A semiconductor device includes a gate structure extending from a first surface of a semiconductor portion into a mesa section between neighboring field electrode structures and an alignment layer formed on the first surface. The alignment layer includes mask pits formed in the alignment layer in a vertical projection of the field electrode structures. Sidewalls of the mask pits have a smaller tilt angle with respect to the first surface than sidewalls of the field electrode structures. The gate structure is in the vertical projection of a gap between neighboring mask pits.

Semiconductor device having an alignment layer with mask pits

A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. A fourth semiconductor region adjoins the first semiconductor layers, is spaced apart from the first semiconductor region, and is arranged in the first device region between the first end of the first semiconductor region and the third semiconductor region.

Semiconductor device having a high breakdown voltage

A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions. An average doping concentration along a shortest path between the first and third semiconductor regions in at least one of the first or second semiconductor layers in the first region differs from an average doping concentration along a shortest path between the first and third semiconductor regions of the same layer in the second region.

A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body and having body regions of a first conductivity type, a drift region of a second conductivity type that is opposite from the first conductivity type and is disposed between the body regions and a second surface of the semiconductor body that is opposite from the first surface, and an emitter layer of the second conductivity type that is disposed between the drift region and a second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region, a metal drain electrode directly adjoining the emitter layer. The metal drain electrode comprises spikes extending into the emitter layer.

Semiconductor device with drain structure and metal drain electrode

A method for forming a superjunction transistor device includes: forming a plurality of semiconductor layers one on top of the other; implanting dopant atoms of a first doping type into each semiconductor layer to form first implanted regions in each semiconductor layer; implanting dopant atoms of a second doping type into each semiconductor layer to form second implanted regions in each semiconductor layer. Each of implanting the dopant atoms of the first and second doping types into each semiconductor layer includes forming a respective implantation mask on a respective surface of each semiconductor layer, and at least one of forming the first implanted regions and the second implanted regions in at least one of the semiconductor layers includes a tilted implantation process which uses an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.

Method for producing a transistor device having a superjunction structure

A semiconductor device includes an electrical device and has an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device. The output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.

Semiconductor devices and methods for forming a semiconductor device

A semiconductor device includes a semiconductor body having a first surface and second surface opposite to the first surface in a vertical direction, and a plurality of transistor cells at least partly integrated in the semiconductor body. Each transistor cell includes at least two source regions, first and second gate electrodes spaced apart from each other in a first horizontal direction and arranged adjacent to and dielectrically insulated from a continuous body region, a drift region separated from the at least two source regions by the body region, and at least three contact plugs extending from the body region towards a source electrode in the vertical direction. The at least three contact plugs are arranged successively between the first and second gate electrodes. Only the two outermost contact plugs that are arranged closest to the first and second gate electrodes, respectively, directly adjoin at least one of the source regions.

Semiconductor device

A semiconductor device includes a semiconductor substrate, a transistor cell region formed in the semiconductor substrate and an inner termination region formed in the semiconductor substrate and devoid of transistor cells. The transistor cell region includes a gate structure extending from a first surface into the semiconductor substrate, a plurality of needle-shaped first field plate structures extending from the first surface into the semiconductor substrate, body regions of a second conductivity type, and source regions of a first conductivity type formed between the body regions and the first surface. The inner termination region surrounds the transistor cell region and includes needle-shaped second field plate structures extending from the first surface into the semiconductor substrate. The needle-shaped first field plate structures are arranged in a first pattern and the needle-shaped second field plate structures are arranged in a second pattern.

Semiconductor device having a transistor cell region and a termination region with needle-shaped field plate structures

Growing community of inventors

Isen, Germany

Franz Hirler