Sanmina-sci Corporation

Flex Ltd.

Multek Technologies Limited

Franz Gisin

George Dudnikov, Jr

Gregory J Schroeder

Mark A Bergman

William Panos

Mahamud Khandokar

Christopher Herrick

A circuit board transmission line structures has microstrip or stripline transmission line geometries and cross-hatch patterned return planes. The cross-hatch design structure of the return planes and the relative position of the cross-hatch pattern to the transmission lines are configured to increase the usable bandwidth of the transmission lines. By properly adjusting the size and shape of the cross-hatch pattern, the performance of the microstrip and stripline transmission lines can be largely restored to the performance where continuous, solid return planes are used.

Stripline transmission lines with cross-hatched pattern return plane, where the striplines do not overlap any intersections in the cross-hatched pattern

A measuring system and method is configured to analyze numerous different types of interconnects having varying degrees of complexity. The measuring system and method characterizes an interconnect to be tested by a predefined reflection coefficient signature. Each specific interconnect is predefined by a reflection coefficient signature that is unique to that specific interconnect. Once the reflection coefficient signature is defined, a corresponding reflection envelope is defined which defines boundary limits about the reflection coefficient signature. Subsequent testing of the specific interconnect results in a measured reflection coefficient curve, which is compared to the corresponding reflection envelope. The specific interconnect under test is considered acceptable if the values of the measured reflection coefficient curve do not fall outside the reflection envelope. If one or more values of the measured reflection coefficient curve fall outside the reflection envelope, then the specific interconnect under test fails the test.

Measuring complex PCB-based interconnects in a production environment

Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

Simultaneous and selective partitioning of via structures using plating resist

The protection of sensitive components on printed circuit boards by using planar transient protection material in one or more layers of a printed circuit board stackup is disclosed.

Substantially continuous layer of embedded transient protection for printed circuit boards

Protection for sensitive components on a printed circuit board by selectively depositing transient protection material on one or more layers of the printed circuit board is disclosed.

Selective deposition of embedded transient protection for printed circuit boards

Vias are used in multilayer printed circuit boards to route electrical interconnects between layers. Some via constructions embodiments result in the formation of a via-stub section. Via stub sections can distort signals passing through the interconnect and decrease the usable bandwidth of the interconnect. To minimize distortion and increase bandwidth, one or more terminating elements can be attached to the unterminated end of the via-stub section. The impedance terminating element may include, by way of non-limiting example, one or more resistors, capacitors, and/or inductors between the via stub and a ground layer. The impedance terminating element may be formed internally to the PCB or mounted to the PCB surface.

Via stub termination structures and methods for making same

A method for enhancing the high frequency signal integrity performance of a printed circuit board (PCB) or backplane is provided. According to one embodiment of the present invention, the method involves the use of S-parameters as the primary cost factors associated with an iterative process to optimize the physical dimensions and shape of a single or a collection of vias within the PCB or backplane. In certain embodiments, the process involves the representation of the via components as equivalent lumped series admittances and impedances, as well as, RLGC sub-circuits upon which basic circuit analysis is performed to optimize secondary characteristics, for example, the maximization of the sub-circuit's resistance and/or the minimization of the sub-circuit's capacitance. The iterative process involves the alteration of physical dimensions and the shape of the via components such that the secondary characteristics are optimized.

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San Jose, CA, United States of America

Franz Gisin