Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Qimonda Ag

Franz Freimuth

Martin Brox

Thilo Schaffroth

Naokazu Miyawaki

Mike A Killian

Christian Sichert

Rainer Bartenschlager

Jens Polney

An integrated circuit comprises a sampling circuit arranged at a data output of an operating section and operated by sampling edges, data packets appearing at the data output in response to a sequence of request commands, and a control section configured to produce the sampling edges, the control section comprising at least two transmission branches each comprising a copy of the operating section. Pulse trains are applied to the transmission branches which have the same waveform as the sequence of request commands and are delayed relative to one another, wherein the first pulse train is contemporaneous with the sequence of request commands. The sampling edges are produced from leading edges of the pulse trains which appear at the outputs of the transmission branches.

Integrated circuit for sampling a sequence of data packets at a data output

A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an 'internal' operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Apparatus for controlling circuit response during power-up

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Munich, Germany

Franz Freimuth