Koninklijke Philips Corporation N.v.

Nvidia Corporation

Nxp B.v.

Frans Sijstermans

Sunny C Huang

Rudolf H J Bloks

Kornelis Antonius Vissers

Stefan Eckart

Jos Van Eijndhoven

Lakshmi Rao

Marcel J A Tromp

Zheng Wei Jiang

Evert-Jan D Pol

Yong Peng

The present invention provides an apparatus for interpolation which is able to process input data with multiple video standards without sacrificing chip area. The interpolation unit comprises: a first interpolation unit for interpolating input data; a second interpolation unit for interpolating input data; a filter indicator for providing information to the first interpolation unit and the second interpolation unit; and an output unit for multiplexing and averaging output from the first interpolation unit and the second interpolation unit. The present invention also provides a motion compensation unit and a decoder for processing multiple video standards.

Two-dimensional interpolation architecture for motion compensation in multiple video standards

Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on the operation mask, the processor selectively executes one or more operations within a second instruction. Individual operations within a multi-operation instruction can be selectively enabled and disabled, which is advantageous in many situations, including event handling and code debugging.

Dynamically controlling execution of operations within a multi-operation instruction

Various methods for performing rounding operations in a computer processor are described. A machine instruction sets the rounding mode, which is automatically applied to subsequent machine instructions. Using machine instructions to round results according to the selected rounding mode has several advantages over software-implemented rounding techniques, such as faster execution and concise code. A variety of rounding modes can be specified. Depending in part on the specified rounding mode and on the sign of the value to be rounded, a rounding term is added to the value to be rounded. Adding this rounding term ensures that the desired result is obtained. The value thus obtained is then right-shifted.

Rounding operations in computer processor

The invention is directed to techniques for managing a cache within a processor using one or more machine instructions. The machine instructions may perform one or more operations on the cache. For example, victimize instructions, allocate instructions, and pre-fetch instructions can be executed in the processor as part of cache management. Moreover, these various cache management instructions may be defined by one or more operands that specify memory addresses within main memory, rather than addresses or identifiers that define locations within the cache. For this reason, a programmer may invoke these cache management instructions to direct the management of the cache without knowing the specific location of data within the cache.

Cache management instructions

A method and system for correctly processing both big endian and little endian vector data. If the vector has a little endian data order, each piece of data (such as a byte) within the vector is processed in order. If the vector has a big endian data order, each vector element is processed in order, but each piece of data within each vector element is processed in reverse order.

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Los Altos, CA, United States of America

Frans Sijstermans