U.S. Philips Corporation

Nxp B.v.

Frans J List

Pim Theo Tuyls

Roger Cuppens

Maarten Vertregt

Hans De Jong

Cathal G Phelan

Cornelis D Hartgring

Mathias Wagner

Maurits Storms

Frank Zachariasse

Arjan Mels

Rob Verhaar

Guido J M Dormans

Robert H Beurze

Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.

Flash- and ROM-memory

It is described a method for providing an electronic key within an integrated circuit () including both a volatile memory () and a non-volatile memory (). The described comprises starting up the integrated circuit (), reading the logical state of predetermined data storage cells () assigned to the volatile memory (), which data storage cells () are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and generating an electronic key by using the logical state of the predetermined data storage cells (). Preferably, the predetermined data storage cells () are randomly distributed within the volatile memory (). It is further described an integrated circuit () for providing an electronic key. The integrated circuit () comprises a volatile memory () comprising predetermined data storage cells (), which are characterized that with a plurality of start up procedures they respectively adopt the same logical state, and a non-volatile memory () having information stored upon regarding the predetermined data storage cells (). Thereby, the electronic key is defined by the corresponding logical states of the predetermined data storage cells ().

Security storage of electronic keys within volatile memories

A memory incorporates redundancy in the form of one or more redundant columns. An applied binary address is first distributed between predecoders which form a 1-out-of-2.sup.n code from n bits received. For each non-redundant column there is available a part of a main decoder, each part receiving a different combination of the bits supplied by the predecoders, thus selecting the column. For each redundant column there is provided a redundancy decoder. The latter decoder receives all bits supplied by the predecoders, each time via a series connection of a activatable gating element and a fuse element. Per predecoder the outputs of the series connections are combined in a wired logic function. Each wired logic function forms an input signal of the actual redundancy decoder. When a redundant column is to be addressed, all fuse elements but one of a group are opened and the gating elements are activated. A memory column to be replaced is then uncoupled by way of another fuse element.

Redundant-storage memory

The invention relates to a (static) memory which is divided into a number of memory blocks, memory cells being arranged in rows and columns in each memory block. A row in a memory block is activated via a selection gate whereto there are applied an inverted row selection signal (which is applied to all memory blocks) and a non-inverted and an inverted block selection signal (which is applied to all section gates in a memory block). The selection gate comprises a P-MOS transistor and two parallel-connected N-MOS transistors. The junction between the P-MOS and the N-MOS transistors constitutes the gate output (for activating a row of cells). The row selection signal is applied to the gate electrode of the PMOS transistor and of a first N-MOS transistor. The inverted block selection signal is applied to the gate electrode of the other N-MOS transistor and the block selection signal is applied to the main electrode of the P-MOS transistor.

Integrated memory circuit having an improved logic row selection gate

Growing community of inventors

Eindhoven, Netherlands

Frans J List