National Semiconductor Corporation

Franklin S Ho

William E Miller

Richard E Crippen

Ying Quan Zhong

A voltage supply circuit for an LCD driver employs two voltage dividers. A low current voltage divider includes resistive elements having a high resistance, thus providing a bias voltage with a low current. A high current voltage divider includes resistive elements having low resistances, thus providing a bias voltage with a high current. The high current voltage divider provides bias voltage levels with high current at the beginning of each time phase change. Thus, the liquid crystal display receives a high current when updating the bias voltage levels on the LCD, thereby producing a fast settling time. When the bias voltage levels are held constant, however, only the low current voltage divider provides the bias voltage levels to reduce power consumption. A halt mode prevents the liquid crystal display and driver from consuming any power by disconnecting both voltage dividers from the voltage source when in sleep mode. A voltage drop mode produces a reduction in the bias voltage levels by placing another voltage drop in series with the voltage dividers.

Low current voltage supply circuit for an LCD driver

A system and method for selecting a post-reset operating mode for a microcontroller. The system of this invention includes a mode indicating means to communicate to the microcontroller the desired post-reset operating mode. These means may include pin(s), and/or bit flags in main memory or register. A mode selection logic circuit receives the mode detector information. If the program code corresponding to the desired operating mode has a starting address in main memory different from the default starting address of the first fetch instruction to the CPU, then the mode selection logic disables the program memory to prevent the first instruction fetch by the CPU, and instead, inserts a surrogate branch instruction onto the data bus causing the CPU to BRANCH to the starting address of the program code corresponding to the desired post-reset operating mode. Re-enabling the program memory after insertion of the surrogate branch instruction permits the CPU to execute the appropriate program code to put the microcontroller in that desired operating mode.

Microcontroller mode selection system and method upon reset

A single resistance permits a CMOS driver to have output devices that controllably transition 'fast off-slow on' and which are not simultaneously on while the driver switches states. The driver's output and supply currents contain reduced harmonics. The resistance is coupled to the gates of the output stage PMOS-NMOS devices, and forms an RC circuit with the intrinsic capacitance at the gates, extending the turn-on transition of the gate drive voltages. Each output device then turns on relatively slowly, but turns off normally. The output current transition times are essentially determined by the resistance and intrinsic capacitances. The resistance is implemented using polysilicon or diffusion, and preferably has a magnitude ten times the on-channel resistance of the input PMOS and NMOS devices driving the output stage. Because the resistance and intrinsic capacitances are essentially temperature and power supply voltage independent, and but slightly process dependent, the current output transition times can be controlled despite CMOS parameter variations. A 3-state embodiment of the CMOS buffer uses parallel coupled PMOS-NMOS devices to switchably couple in the resistance between both output gates when the enable signal is high. Second input PMOS and NMOS devices, connected in parallel across the first input PMOS and NMOS devices, turn on across the first input devices when the enable signal is low. A high enable signal enables the driver circuit, while a low enable signal uncouples the resistance and turns off both output PMOS and NMOS devices, putting the circuit's output in a high impedance state.

Growing community of inventors

San Carlos, CA, United States of America

Franklin S Ho