Oracle International Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

Frankie Liu

Suwen Yang

Ronald Ho

Eric Y Chang

Philip Amberg

Dinesh D Patil

Ashok V Krishnamoorthy

Guanghua Shu

Saman Saeedi

Ziad Saleh Shehadeh

Xuezhe Zheng

Elad Alon

Robert David Hopkins

Thomas Germano O'Neill

Robert J Drost

John E Cunningham

Guoliang Li

Dawei Huang

Ivan Shubin

Rajesh Kumar

Hiren D Thacker

Robert David Hopkins, Ii

Jon Lexau

Vincent Lee

Kunmo Kim

Phillip Kwan

Xiaolei Li

Yue Zhang

A method and apparatus for correcting baseline wander is disclosed. The method and apparatus may include generating filtered signals by filtering input signals using a filter circuit. An equalizer circuit using the filtered signals may generate output signals. Feedback networks may be configured to couple a respective output signal to a corresponding filtered signal.

Baseline wander correction in AC coupled communication links using equalizer with active feedback

The disclosed embodiments relate to the design of a temperature sensor, which is integrated into a semiconductor chip. This temperature sensor comprises an electro-thermal filter (ETF) integrated onto the semiconductor chip, wherein the ETF comprises: a heater; a thermopile, and a heat-transmission medium that couples the heater to the thermopile, wherein the heat-transmission medium comprises a polysilicon layer sandwiched between silicon dioxide layers. It also comprises a measurement circuit that measures a transfer function through the ETF to determine a temperature reading for the temperature sensor.

CMOS thermal-diffusivity temperature sensor based on polysilicon

We disclose a system, which performs a duty-cycle correction operation for an injection-locked phase-locked loop (PLL). The system first obtains a pattern of positive and negative error pulses at rising and falling edges of a reference clock signal for the injection-locked PLL, wherein the pattern specifies deviations of the reference clock signal from a 50% duty cycle. The system multiplies the pattern of positive and negative error pulses by a duty-cycle distortion (DCD) template, which specifies a sign of a duty-cycle error for the reference clock signal, to calculate duty-cycle distortion values. The system then accumulates the duty-cycle distortion values to produce a duty-cycle-error amplitude. Next, the system multiplies the duty-cycle-error amplitude by the DCD template to produce a duty-cycle correction signal. Finally, the system uses the duty-cycle correction signal to compensate for timing errors in the injection-locked PLL, which are caused by duty-cycle variations in the reference clock signal.

Digitally assisted feedback loop for duty-cycle correction in an injection-locked PLL

A voltage-controlled oscillator (VCO) having an LC tank circuit with a variable inductance is disclosed. In one embodiment, the VCO includes a capacitance, at least a portion of which is variable and responsive to a first tuning voltage. The VCO further includes a transformer having first (primary) and second (secondary) windings. The primary winding is coupled to the capacitance, and provides the inductance of the LC tank circuit. The secondary winding is coupled to a current control circuit. The current control circuit may vary the induced current through the secondary winding. By varying the induced current through the secondary winding, the effective inductance of the primary winding may also be varied. Accordingly, the VCO may be tuned by varying the inductance of the LC tank circuit, as well as by varying the capacitance of the same.

Voltage controlled oscillator with tunable inductor and capacitor

The disclosed embodiments relate to a system that controls a phase-locked loop (PLL), eliminating harmonic locking issues during subsampling operation and achieving better noise performance. During operation, the system performs a procedure to measure a first duty cycle that indicates a relationship between a reference signal, which has a frequency F, and a voltage-controlled oscillator (VCO) output signal, which has a frequency Fand is generated by a VCO. The system also performs the procedure to measure a second duty cycle that indicates a relationship between a second reference signal (with a frequency of c*F) and the VCO-output signal. Next, the system determines a frequency and phase relationship between the reference signal and the VCO-output signal based on the first and second duty cycles. Finally, the system uses the frequency and phase relationship to adjust the VCO so that the VCO-output signal, which is used as an output of the PLL, is frequency and phase aligned with the reference signal.

Subsampling phase frequency detector for a divider-less phase-locked loop

In an optical device, a ring-resonator modulator, having an adjustable resonance (center) wavelength, receives an optical signal that includes a carrier wavelength from an input-output optical waveguide. Then, a monitoring mechanism monitors a performance metric (such as an average power or a signal swing) of a monitor optical signal from the ring-resonator modulator. Moreover, control logic in the optical device adjusts the resonance wavelength based on the monitored performance metric so that the resonance wavelength is locked to the carrier wavelength. In particular, the control logic may apply a change to an adjustment signal that is provided to the ring-resonator modulator. If the change increases the performance metric, the control logic may continue to modify the resonance wavelength. Otherwise, the control logic may modify the resonance wavelength by applying one or more changes, having an opposite sign to the change, to the adjustment signal.

In-situ ring-resonator-modulator calibration

During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator. Finally, the system uses a gating mechanism to periodically suppress the injected pulses produced by the injection pulse generator to enable the frequency-tracking path to detect and remediate frequency errors without interference from phase adjustments.

Injection-locking PLL with frequency drift tracking and duty-cycle distortion cancellation

In the optical device, a ring-resonator modulator, having an adjustable resonance (center) wavelength, optically couples an optical signal that includes the carrier wavelength from an input optical waveguide to an output optical waveguide. A monitoring mechanism in the optical device, which is optically coupled to the output optical waveguide, monitors a performance metric of an output optical signal from the output waveguide. For example, the monitoring mechanism may monitor: an average optical power associated with the output optical signal, and/or an amplitude of the output optical signal. Moreover, control logic in the optical device adjusts the resonance wavelength based on the monitored performance metric so that the performance metric is optimized.

Wavelength-locking a ring-resonator modulator

An optical receiver receives a photocurrent from a photosensor and uses a transimpedance element to convert the photocurrent into an input signal. Next, an amplifier amplifies the input signal to produce an amplified input signal. At the same time, a clock-recovery circuit generates a clock signal, which is used to clock the amplified input signal to produce a receiver output. During an initial-calibration operation, the clock-recovery circuit phase-aligns a locally generated reference signal with transitions in the amplified input voltage signal to produce the clock signal by: feeding the reference signal through a delay-locked loop to produce a set of equally spaced phases; using the set of equally spaced phases to sample a preamble in the amplified input voltage signal to detect a crossing point; choosing a corresponding phase from the set of equally spaced phases based on the crossing point; and using the chosen phase to produce the clock signal.

Burst-mode optical receiver with feed-forward DC-bias acquisition and flash-oversampling clock recovery

An optical receiver receives a photocurrent from a photosensor and uses a transimpedance element to convert the photocurrent into an input voltage signal. An amplifier then amplifies the input voltage signal to produce a receiver output. During this process, a reference-voltage-generation circuit generates a reference voltage for the amplifier. This reference-voltage-generation circuit includes a data-detection circuit that detects data on the input voltage signal, and an adjustable low-pass filter, which filters the input voltage signal to produce the reference voltage. During a faster operating mode, which occurs when the data-detection circuit does not detect data on the input voltage signal, the filter has a cutoff frequency f. During a slower operating mode, which starts a bias-delay time tafter the data-detection circuit detects data on the input voltage signal, and lasts until the data-detection circuit no longer detects data, the filter has a lower cutoff frequency f.

Feed-forward DC-bias acquisition for burst-mode optical receivers

In an integrated circuit, a resettable data latch and a second resettable data latch at ends of a pipeline in a frequency-comparison circuit receive input clocks. This pipeline operates asynchronously and includes at least a pair of flow-control elements separated by a NAND-gate detector circuit. Moreover, the resettable data latch and the second resettable data latch selectively generate tokens and spaces based on rising or falling edges of the input clocks. Then, the frequency-comparison circuit moves the tokens and the spaces in the pipeline between the ends based on a difference in fundamental frequencies of the input clocks. Furthermore, arbiter circuits in the frequency-comparison circuit provide output signals based on changes in numbers of tokens proximate to the ends, to indicate how at least one of the input clocks should be adjusted so that the fundamental frequencies converge on a common value.

Micro-pipeline frequency-comparison circuit

An optical receiver includes a feedback circuit that applies a feedback signal to a front-end circuit prior to the front-end circuit converting an optical signal into an analog electrical signal. In particular, the optical receiver includes a digital slicer that determines a digital electrical signal from the analog electrical signal based on a reference voltage that specifies a decision threshold and a clock that specifies sampling times. The feedback circuit determines the feedback signal at least one previous bit preceding a current bit in the analog electrical signal that is provided by the digital slicer and an impulse response of a communication channel. Moreover, the feedback signal has a pulse width that is less than a bit time of the clock. In this way, the optical receiver can cancel post-cursors of the current bit, even when the communication channel includes a low-pass filter.

Optical receiver with adjustable pulse-width feedback

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit by a top surface of the interposer, where the top surface faces the front surface of the integrated circuit and the front surface of the optical integrated circuit. Furthermore, the integrated circuit and the optical integrated circuit may be on a same side of the interposer. By integrating the optical integrated circuit and the integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Hybrid-integrated photonic chip package with an interposer

A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line.

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Palo Alto, CA, United States of America

Frankie Liu