Micron Technology Incorporated

Micron Quantum Devices Inc.

Round Rock Research, LLC

Other

Micro Technology, Inc.

Mircon Technology, Inc.

Micron Tehnology, Inc.

Frankie F Roohparvar

Vishal Sarin

Jung-Sheng Hoei

Tommaso Vali

Luca De Santis

Ebrahim Abedifard

Kenneth James Eldredge

Jung Sheng Hoei

Kevin Widmer

Cliff Zitlaw

Christophe J Chevallier

Jonathan Pabustan

Dean K Nobunaga

Michael S Briner

William Henry Radke

Benjamin S Louie

Dzung Huu Nguyen

David A Eggleston

Violante Moschiano

Giovanni Santin

Giulio Giuseppe Marotta

Agostino Macerola

Marco-Domenico Tiburzi

Allahyar Vahidimowlavi

Adam D Johnson

Clifford Alan Zitlaw

Dumitru G Cioaca

William Saiki

Giulio-Giuseppe Marotta

Scott N Gatzemeier

Darrell D Rinerson

Chia-Shing Jason Yu

Al Vahidimowlavi

A Papaliolios

Fred Jaffin, Iii

Al Vahidi-Mowlavi

Tomasso Vali

Kevin C Zitlaw

Abrahim Abedifard

A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.

Memory devices for comparing input data to data stored in memory cells coupled to a data line

Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.

Memory configured to perform logic operations on values representative of sensed characteristics of data lines and a threshold data value

Non-volatile memory having a non-volatile memory array adapted to store a configuration routine for a low power dynamic random access memory (LPDRAM), a memory interface for receiving addresses from an external device for access of data stored in the non-volatile memory array, and an internal controller adapted to communicate with a LPDRAM coupled to the non-volatile memory and configure operational settings of the LPDRAM using the configuration routine, as well as systems containing similar non-volatile memory.

Non-volatile memory adapted to configure low power dynamic random access memory

Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

Memory devices for pattern matching

Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.

Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.

Memory configured to generate a data value from a data line connected to more than one string of series-connected memory cells

Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

Configurable operating mode memory device and methods of operation

Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.

Memory as a programmable logic device

Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

Methods of operating memory

Memories including a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, as well as methods of operating similar memories.

Growing community of inventors

Monte Sereno, CA, United States of America

Frankie F Roohparvar