Micron Technology Incorporated

Micron Quantum Devices Inc.

Frankie E Roohparvar

Vishal Sarin

Jung Sheng Hoei

A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.

Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells

Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell.

Non-volatile multilevel memory cells with data read of reference cells

An integrated memory circuit (chip) and methods for testing the chip. The chip has an array of memory cells, a sense amplifier for reading selected ones of the cells, and a switch having a first state allowing an external device connected to an external pad to sink a reference current from the sense amplifier and a second state disconnecting the pad from the sense amplifier (so that an internally generated reference current can be supplied to the sense amplifier with the switch in the second state). In the first state, the switch preferably is tolerant of a broad and continuous range of voltages on the pad. In some test modes, cells are read using a sense amplifier of the chip while selected voltages are applied to each cell and external equipment sinks reference current flowing from the sense amplifier through an external pad, thus sensing data from each cell with all the timing constraints usually placed on a read of the cell in the normal mode. In one test mode, all wordlines of the array are disabled and a read cycle is performed to measure all columns of the array sequentially while an external reference current flows between external test equipment and a sense amplifier used for performing the read cycle, and the sense amplifier output indicates whether one or more of the columns has leaky cells.

Circuit and method for performing tests on memory array cells using external sense amplifier reference current

Circuit and method for performing test on memory array cells using

A controllable one-shot circuit for use in a control unit of a memory circuit, for asserting a control signal with variable (and controllable) duration in response to a trigger signal, and a state machine for controlling memory operations of a memory circuit which includes such a controllable one-shot circuit. In preferred embodiments, the one-shot and the state machine of which it is a part are implemented as parts of a single memory chip (preferably, a nonvolatile memory chip such as an integrated flash memory circuit). Other aspects of the invention are methods of operating a state machine of a memory circuit to generate control signals for use in controlling memory operations performed by the memory circuit. In preferred embodiments of such methods, the state machine is included in an integrated memory circuit and the one-shot circuit is controlled to assert a control signal with a desired duration in response to a trigger signal, thus enabling the state machine to control efficiently the duration of selected memory operations (or sub-operations of such operations) of the memory circuit.

Controllable one-shot circuit and method for controlling operation of

Circuit and method for performing tests on memory array cells using

A data input/output circuit used to program the cells of a memory array or to determine the state of those cells. The circuit includes a data write path used for programming the memory cells in the array and a data read path for reading data indicative of the state of the cells. The data write path includes switching means for electrically disconnecting the high capacitance elements of the write path from the read path. The switching means is under the control of a control means which acts to enable or disable the switching means. The switching means serves to electrically isolate the high capacitance elements of the write path from the read path, thereby increasing the speed with which a read operation be performed.

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Cupertino, CA, United States of America

Frankie E Roohparvar