Super Talent Electronics, Inc.

Super Talent Technology, Corp.

Frank Yu

Abraham C Ma

Charles Chung Lee

Shimon Chen

Ming-Shiang Shen

David Q Chow

Yi Syu Yan

Yao-Tse Chang

Jim Chin-Nan Ni

Yan Zhou

Horng-Yee Chou

Tzu-Yih Chu

Myeongjin Shin

A Green NAND Device (GND) driver application queries AC line and battery status and then stores an image of processor states and caches and a resume routine to DRAM when power failure occurs. A DRAM image is then stored to flash memory for a persistent mode when battery power is available. The image in DRAM may be a partial image that includes entries, flushed caches, processor contexts, ramdisks, write caches, and a resume context. Endurance of flash memory is increased by a Super Enhanced Endurance Device (SEED) SSD. In a power down mode, the GND driver limits DRAM use and only caches in DRAM data that can be deleted on power down. Host accesses to flash are intercepted by the GND driver and categorized by data type. Paging files and temporary files cached in DRAM are optionally written to flash.

Green NAND device (GND) driver with DRAM data persistence for enhanced flash endurance and performance

A Green NAND SSD Driver (GNSD) driver executes on a host to increase data-retention of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the GNSD driver using upper and lower-level filter drivers. A retention-check timer causes a retention routine to be periodically executed. The routine sends high-level commands to the SEED that causes the SEED to refresh either all data or just data blocks with older write dates. Data is refreshed by moving to a new physical block. The retention routine can track write dates of logical blocks and command a SSD to move logical blocks with older write dates. A retention card has a controller that performs the retention routine when not connected to a host, while a SEED power card allows the SEED to refresh data when no host is attached to the SEED.

Data-retention controller/driver for stand-alone or hosted card reader, solid-state-drive (SSD), or super-enhanced-endurance SSD (SEED)

A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Endurance translation layer (ETL) and diversion of temp files for reduced flash wear of a super-endurance solid-state drive

A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. Ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Virtual memory device (VMD) application/driver for enhanced flash endurance

A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD.

Green NAND SSD application and driver

A controller for a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD) increases flash endurance using a DRAM buffer. Host accesses to flash are intercepted by the controller and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type in the DRAM before storage by lower-level flash devices such as eMMC, UFS, or iSSD. Caches in the DRAM buffer for storing each data type are managed and flushed to the flash devices by the controller. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Green eMMC device (GeD) controller with DRAM data persistence, data-type splitting, meta-page grouping, and diversion of temp files for enhanced flash endurance

A GNSD (Green NAND Solid State Drive) Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES (Data Encryption Standard) or AES (Advanced Encryption Standard). A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an (Super Enhanced Endurance Device) SEED SSD (Solid State Drive).

An retention flash controller reads assigned-level bits from a bad block/erase count table or from a page status table that indicate when flash memory cells operate as Triple-Level-Cell (TLC), Multi-Level-Cell (MLC), or Single-Level-Cell (SLC). Pages that fail as TLC or MLC are downgraded for use as SLC pages by changing the assigned-level bits. The level bits adjust truth tables used by translation logic that receives inputs from voltage comparators reading a bit line. The range of voltages for each logic level may be adjusted by the truth tables or by programmable registers. The programming voltage or programming pulses may be adjusted to increase endurance and the number of permitted program-erase cycles while reducing retention times before a refresh is needed of the flash cells. Mixed configurations of flash memory have MLC blocks and MLC as SLC blocks, or other combinations.

Endurance and retention flash controller with programmable binary-levels-per-cell bits identifying pages or blocks as having triple, multi, or single-level flash-memory cells

Super-endurance solid-state drive with endurance translation layer (ETL) and diversion of temp files for reduced flash wear

A Virtual-Memory Device (VMD) driver and application execute on a host to increase endurance of flash memory attached to a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD). Host accesses to flash are intercepted by the VMD driver using upper and lower-level filter drivers and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type before storage by the SSD. ramdisks and caches for storing each data type in the host DRAM are managed and flushed to the SSD by the VMD driver. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.

Virtual memory device (VMD) application/driver with dual-level interception for data-type splitting, meta-page grouping, and diversion of temp files to ramdisks for enhanced flash endurance

A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.

Flash-memory device with RAID-type controller

A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.

Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read

A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

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Palo Alto, CA, United States of America

Frank Yu