Agere Systems Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Frank Yauchee Hui

Edward Belden Harris

Michael Scott Carroll

Allen Yen

Tony G Ivanov

Yifeng Winston Yan

Robert Y S Huang

A fusible link formed on a semiconductor substrate. The fusible link comprises a silicide layer overlying a polysilicon layer. The fusible link is programmed to an open state by passing a current therethrough that opens the polysilicon and the silicide layers.

Method and apparatus for using cobalt silicided polycrystalline silicon for a one time programmable non-volatile semiconductor memory

An apparatus and method for identifying integrated circuit chips or dice on a semiconductor wafer. Each chip comprises a ring oscillator having a characteristic oscillating frequency different from the oscillating frequency of the ring oscillators of other chips on the same wafer. Each chip can be associated with various attributes of the wafer on which it was formed and the process steps to which it was subjected using the ring oscillator frequency.

Method and apparatus using an on-chip ring oscillator for chip identification

A monolithic integrated circuit including a capacitor structure. In one embodiment the integrated circuit includes at least first and second levels of interconnect conductor for connection to a semiconductor layer and a stack of alternating conductive and insulative layers formed in vertical alignment with respect to an underlying plane. The stack is formed between the first and second levels of conductor. Preferably the stack includes a first conductive layer, a first insulator layer formed over the first conductive layer, a second conductive layer formed over the first insulative layer, a second insulator layer formed over the second conductive layer, and a third conductive layer formed over the second insulative layer, with the first and third conductive layers commonly connected.

Stacked structure for parallel capacitors and method of fabrication

A fuse for use in an integrated circuit includes a dielectric layer into which a trench or void is etched defined by a top opening and a bottom floor. The trench includes at least one undercut which forms an overhang in the dielectric layer partially shielding the bottom floor. A second or barrier layer deposited onto the dielectric layer is interrupted or non-continuous at the undercut. A third, or electrically conductive layer, is electrically continuous over the fuse. A weak spot in the third layer exists in the lack of structural support by the second layer at the interruption. A further weak spot in the third layer exists in the electrical isolation of the conductor layer, i.e. no leakage current through the barrier layer, at the interruption.

Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation

A resistor fuse for use in a semiconductor device having an operating voltage. In one embodiment, the resistor fuse includes a silicon layer located over a semiconductor wafer and a metal silicide layer located over the silicon layer. The resistor fuse has a predetermined current threshold and is configured to open if a current through the resistor fuse at the operating voltage exceeds the current threshold.

Growing community of inventors

Orlando, FL, United States of America

Frank Yauchee Hui