Cadence Design Systems, Inc.

Frank X Farmar

Sean Bergan

Randall Scott Lawson

Brett Allen Neal

Richard Allen Woodward, Jr

Jelena Radumilo-Franklin

Joseph Dexter Smedley

Paul S Musto

Gregory M Horlick

Taranjit Singh Kukal

Vikas Kohli

Steven Roberts Durrill

Patrick Bernard

Brian James Carlson

George Malcolm Buzzell

Edmund J Hickey

Chris Cheung

Keith Felton

Robert Paul White

Amey Vilas Joshi

The present disclosure relates to a system and method for modeling the placement of components in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design at a graphical user interface (GUI) and a selection for a component to be placed within the electronic circuit design. Embodiments may also include detecting a change in the position of the selected component to determine when the selected component is moved into a zone of the electronic circuit design. Embodiments may further include determining a component footprint and one or more padstacks associated with the component footprint for the selected component based upon the position of the selected component within the zone of the electronic circuit design. Embodiments may also include rendering the component footprint and the padstacks on the selected component based upon, at least in part, the position of the selected component.

System and method for placing components in an electronic circuit design

The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include implementing the change to the electronic circuit design at the client computing device without receiving authorization from a server computing device and transmitting the implemented change to the electronic circuit design to the server computing device.

Concurrent design process

A system and method are provided for establishing an automated routing environment in an electronic design automation (EDA) work flow for the routing of a circuit design. A user may merely specify a flow via pattern, a flow via location, and a start and end terminal and thereby, the auto router or path finder will automatically find the least-cost paths between each of the start terminals through at least one intermediate via of the flow via and ending at an end terminal. Upon successful routing of all needed terminals, an at least partially routed circuit design may be output.

Method and system for routing optimally between terminals through intermediate vias in a circuit design

A method of interconnecting a first plurality of electronic components and a second plurality of electronic components to form an electronic circuit includes exporting a first netlist representing a first interconnection of the first electronic components in a first design entry tool, exporting a second netlist representing a second interconnection of the second electronic components in a second design entry tool, providing at least a first interface from the second plurality to the first plurality in the second design entry tool, populating the first interface through the first design entry tool, and exporting a third netlist representing the first interface from the second plurality to the first plurality from the second design entry tool, wherein the third netlist stitches the first netlist to the second netlist.

Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout

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Amherst, NH, United States of America

Frank X Farmar