Actel Corporation, Inc.

Microsemi Soc Corporation

Other

Texas Tech University System

Frank W Hawley

John L McCollum

Jonathan W Greene

Abdelshafy A Eltoukhy

A Farid Issaq

Fethi Dhaoui

Yeouchung Yen

Ying W Go

Leslie Richard Wilkinson

Abdul R Forouhi

Steve S Chiang

Hung-Sheng Chen

Wenn-Jei Chen

Jin Miao Shen

Shubhra M Gangopadhyay

Jorge A Lubguban

Zhigang Wang

Michael Alan Sadd

Jeewika Ranaweera

Yen Yeouchung

Farid Issaq

A resistive random-access memory device formed on a semiconductor substrate includes a first interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via has a top surface extending above a top surface of the chemical-mechanical-polishing stop layer. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer extend beyond outer edges of the first via. A second interlayer dielectric layer including a second via is formed over the dielectric layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.

Front to back resistive random-access memory cells

A resistive random-access memory device formed on a semiconductor substrate includes an interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via presents a substantially planar top surface. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer form an aligned stack having edges extending beyond outer edges of the first via. A dielectric barrier layer including a second via is formed over the aligned stack and at least a portion of the chemical-mechanical-polishing stop layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.

Front to back resistive random access memory cells

A layout arrangement for a resistive random access memory cell includes an active area, a polysilicon row address line over the active region, a metal column address line running orthogonal to the row address line and having an active region contact portion extending over the active region and having a contact to the active region. A metal output line runs parallel to the column address line over the active region. A first cell contact region intersects with the output line and has a contact to the active region. A first metal cell contact region forms an intersection with the first cell contact region. A first resistive random access memory device is formed at the intersection of the first cell contact region and the output line. A second resistive random access memory device is formed at the intersection of the first cell contact region and the first cell contact region.

Resistive random access memory cells

A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

Non-volatile programmable memory cell and array for programmable logic array

Layouts for resistive RAM cells

A resistive random access memory cell formed in an integrated circuit includes first and second resistive random access memory devices, each including an anode and a cathode. The anode of the second resistive random access memory device is connected to the anode of the first resistive random access memory device. A programming transistor has a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anodes of the first and second resistive random access memory devices, and a gate connected to a program-enable node.

Back to back resistive random access memory cells

A resistive random access memory cell formed in an integrated circuit includes a first resistive random access memory device including an anode and a cathode, a second resistive random access memory device including an anode and a cathode, the cathode of the second resistive random access memory device connected to the anode of the first resistive random access memory device, a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device, and a gate connected to a program-enable nod, and at least one switch transistor having a gate connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device.

A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.

A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.

Resistive RAM devices for programmable logic devices

A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.

Push-pull FPGA cell

Non-volatile programmable memory cell for programmable logic array

A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

Growing community of inventors

Campbell, CA, United States of America

Frank W Hawley