University of California

Nec Corporation

Frank Vahid

Tony Givargis

Jörg Henkel

Susan Lysecky

Gregory Michael Stitt

Roman Lev Lysecky

Stand-alone modules or blocks for use in creating low-power sensor-based monitor/control systems. Each module performs a pre-defined function, and when included in a monitor/control network operates as a node on the network and automatically communicates with one or more connected nodes using a uni-directional packet-based protocol. One class of such predefined nodes communicates Boolean values, for example, with input sensor nodes detecting the presence or absence of environmental phenomena (e.g., motion, light, sound, water, button presses, etc.), intermediate nodes transforming those Boolean values using combinational or sequential logic, and output nodes converting the resulting Boolean values to environmental phenomena (e.g., beeping, light, electric relay activation, etc.) or to data for further processing by a computer. Another class of nodes communicates integer or number values.

Embedded electronics building blocks for user-configurable monitor/control networks

A warp processor includes a microprocessor, profiler, dynamic partitioning module, and warp configurable logic architecture. The warp processor initially executes a binary for an application entirely on the microprocessor, the profiler monitors the execution of the binary to detect its critical code regions, and the dynamic partitioning module partitions the binary into critical and non-critical code regions, re-implements the critical code regions in the configurable logic, and then transforms the binary so that it accesses the configurable logic rather than execute the critical code regions.

Warp processor for dynamic hardware/software partitioning

A method for reducing power consumption by using power estimation data obtained from at the gate-level for a core's representative input stimuli data (instructions), and propagating the power estimation data to a higher (object-oriented) system-level model, which is parameterizable and executable. Depending on the kind of cores, various parameterizable look-up table techniques are used to facilitate self-analyzing core models. As a result, the method is faster than gate-level power estimation techniques and power-related system-level design decisions.

Growing community of inventors

Corona, CA, United States of America

Frank Vahid