Applied Materials, Inc.

Rise Technology, Inc.

Frank Tzen-Wen Guo

Angada Bangalore Sachid

She-Hwa Yen

Bhuvaneshwari Ayyagari-Sangamalli

Blessy Alexander

Sathyanandan Rajivan

Tzu-Chien Hung

Yat Fai Lam

A selector for a memory cell in a memory array may operate by opening different conductive paths to high and low voltages during set and reset operations. A first transistor may open a conductive path between a high voltage and a terminal of the memory element during a reset operation. Similarly, a second transistor may open a conductive path between a low voltage and the terminal of the memory element during a set operation. Some implementations may add a third transistor in series with the first transistor and a fourth transistor in series with the second transistor. The gates of the third and fourth transistors may be biased at a voltage that is about halfway between the low and high voltages. This selector may use smaller transistors while still facilitating high-voltage set and reset operations on resistive memory elements.

Memory cell selector for high-voltage set and reset operations

A sense amplifier reference is generated with the same memory cell columns as data cells in order to match signal paths between the data and reference signals. Each row of data memory cells may have a corresponding set of reference cells, which greatly reduces the number of data cells supported by a reference, and in turn reduces the impact of process variations. A memory array may include data columns, a first reference column in the memory array configured to provide a logic 0 reference signal, and a second reference column in the memory array configured to provide a logic 1 reference signal. A circuit is configured to combine at least the logic 0 reference signal and the logic 1 reference signal to generate a reference signal for a sense amplifier to identify the data signal provided from the data columns.

Reference generation for narrow-range sense amplifiers

Various arrangements for performing successive vector-matrix multiplication may include sequentially performing a first vector-matrix multiplication operation for each bit-order of values in an input vector. The first vector-matrix multiplication operation for each bit-order may generate an analog output. For each analog output generated by the vector-matrix multiplication operation, an analog output may be converted into one or more digital bit values, and the one or more digital bit values may be sent to a second vector-matrix multiplication operation.

Successive bit-ordered binary-weighted multiplier-accumulator

Various arrangements for performing vector-matrix multiplication are provided here. Digital input vectors that include binary-encoded values can be converted into a plurality of analog signals using a plurality of one-bit digital to analog converters (DACs). Using an analog vector matrix multiplier, a vector-matrix multiplication operation can be performed using a weighting matrix for each bit-order of the plurality of analog signals. For each performed vector-matrix multiplication operation, a bit-ordered indication of an output of the analog vector matrix multiplier may be stored. A bit-order weighted summation of the sequentially performed vector-matrix multiplication operation may be performed.

Bit-ordered binary-weighted multiplier-accumulator

A memory circuit may include a memory array, and the memory array may include a plurality of data columns. The plurality of data columns may be configured to store data bits and provide data signals when selected by a read operation. The memory array may also include one or more reference columns distributed in the memory array and configured to provide a reference signal. The reference signal may track with process, voltage, and temperature variations that are specific to the memory array, and may be used to remove a common signal component and adjust the signal level to distinguish between logic 0 and logic 1 data signals.

Narrow range sense amplifier with immunity to noise and variation

A memory circuit includes a memory array with one or more reference columns providing a reference signal and a data column providing a data signal when selected by a read operation. The memory circuit also includes a first circuit that removes a common signal component from the reference signal and from the data signal, along with a second circuit that adjusts the reference signal to be between a logic 1 signal level and a logic 0 signal level. The memory circuit also includes a sense amplifier that determines whether the data signal represents a logic 1 or a logic 0 using the reference signal after the common signal component is removed and after being adjusted, along with the data signal after having the common signal component removed.

The present invention discloses a voltage shifter capable of interfacing between two circuitry each is operating in different voltage range. The voltage shifter comprises an input buffer for converting an external input signal switching within a high voltage range to an internal input signal switching within a low voltage range, an output driver for converting an internal output signal switching within the low voltage range to an external output signal switching within the high voltage range; and a reference voltage generator for generating a reference voltage to the input buffer and the output driver. In addition, the voltage shifter is designed such that each of the transistors within is protected against voltage breakdown so that the voltage shifter can be built by transistors using the low voltage process.

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Danville, CA, United States of America

Frank Tzen-Wen Guo