Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Frank T Hady

Mason B Cabot

Mark B Rosenbluth

John Beck

Blaise B Fanning

Shekoufeh Qawami

Raymond Scott Tetrick

Bryan K Casper

Stephen R Mooney

James E Jaussi

Kiran Pangal

George Vergis

Howard L Heck

Paul D Ruby

Prashant S Damle

Kevin B Stanton

Sowmiya Jayachandran

Emily P Chung

Sanjeev N Trika

Rick Coulson

Brad W Hosler

John W Carroll

Glenn J Hinton

Debabani Choudhury

Amber D Huffman

Kalpesh Dhanvantrai Mehta

Dale J Juenemann

Brendan Traw

James A Boyd

Thomas J Barnes

Oscar P Pinto

David Lawrence Tennenhouse

James Chapple

C Brendan Traw

Anthony S Bock

Scott Burridge

Scott R Tetrick

Jim Chu

An apparatus is described. The apparatus includes a mass storage device processor that is to behave as an additional general purpose processing core of a computing system that a mass storage device having the mass storage device processor is to be coupled to, wherein, the mass storage device processor is to execute out of a component of main memory within the mass storage device.

Coherent multiprocessing enabled compute in storage and memory

A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.

Load reduced nonvolatile memory interface

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Caching for heterogeneous processors

Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Multi-level memory with direct access

An apparatus is described. The apparatus can include non-volatile memory, an embedded processor, and a memory controller. The memory controller can access data from the byte addressable non-volatile memory using at least one of: a first addressing scheme or a second addressing scheme. The memory controller can provide the data to a host system over a first interface when the data is accessed using the first addressing scheme. The memory controller can provide the data to the embedded processor over a second interface when the data is accessed using the second addressing scheme.

Method and apparatus to provide both storage mode and memory mode access to non-volatile memory within a solid state drive

In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Managing disturbance induced errors

Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a first set of contacts, a second set of contacts connected to the one or more signaling circuits, and logic to receive a configuration command. The logic may also connect the first set of contacts to the voltage regulator if the configuration command corresponds to a first protocol. If the configuration command corresponds to a second protocol, on the other hand, the logic can connect the first set of contacts to the one or more signaling circuits.

Interchangeable power and signal contacts for IO connectors

Provided are an apparatus and method for processing sequential writes to a block group of physical blocks in a memory device. Sequential write data for a plurality of consecutive logical addresses is received and a determination is made of consecutive physical blocks comprising a block group. Each of the physical blocks has data for a plurality of the consecutive logical addresses. The sequential write data is written to consecutive physical data locations having data for the determined consecutive physical blocks of the block group. The block group metadata for the block group is updated.

Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device

Provided are an apparatus and method for processing sequential writes portions of an addressable unit memory dies to store data. A write to a first portion of an addressable unit is received and the write is written to the first portion of the addressable unit. A next write is received to a next portion of the addressable unit following a previous write to a previous portion of the addressable unit. The next write is written to the next portion of the addressable unit sequentially following the previous portion in response to the next write being sequential with respect to the previous write. Data other than the next write is written to the addressable unit following the previous portion in response to the next write not being sequential with respect to the previous write.

Method and apparatus for processing sequential writes to portions of an addressable unit

Systems and methods of interconnecting devices may include an input/output (IO) connector having a buffer with an integrated voltage regulator. The integrated voltage regulator may include a first supply output and a second supply output, wherein the IO connector includes an IO power contact coupled to the first supply output. The IO connector may also include a logic power contact coupled to the second supply output. In one example, a host device may issue power management commands to the buffer in order to scale the second supply output independently of the first supply output.

Host controlled IO power management

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Portland, OR, United States of America

Frank T Hady