Micron Technology Incorporated

Frank Speetjens

Dave Pratt

Raju Ahmed

Yung-Ta Sung

David A Kewley

Yi Hu

Andrew Li

Wei Yeeng Ng

Gurpreet S Lugani

Aaron Kenneth Belsher

Darin Miller

Rajesh Balachandran

Siva Naga Sandeep Chalamalasetty

Allen R Gibson

Sukhdeep Kaur

Sangeetha P Komanduri

Tom Jibu John

S M Istiaque Hossain

Yucheng Wang

Brendan Flynn

Jeremy Adams

Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

Conductive interconnects and methods of forming conductive interconnects

A microelectronic device includes tiers of alternating dielectric and conductive materials, a cap oxide material vertically adjacent to the tiers, and pillars extending vertically through the tiers. The cap oxide material is formulated to exhibit a different etch rate relative to an etch rate of the oxide material of the tiers. Additional microelectronic devices, microelectronic systems, and methods of forming a microelectronic device are also disclosed.

Microelectronic devices including a selectively removable cap dielectric material, methods of forming the microelectronic devices, and related systems

A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.

Systems and methods for mitigating crack propagation in semiconductor die manufacturing

Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

Growing community of inventors

Boise, ID, United States of America

Frank Speetjens