Intel Corporation

Frank S Smith

Glenn J Hinton

Adrian L Carbine

James M Arnold

Truong Nguyen

Sunil R Shenoy

Scott B Huck

Randy L Steck

An instruction decoder that issues new instructions by driving a machine bus ( ) with the correct information during each clock cycle. This information is either extracted from the current instruction to be executed, or is recycled from the previous contents ( ) of the machine bus when a scoreboarding operation has been performed. Mousetrap multiplexer ( ) chooses between several sources of opcode and operand fields and routes them to the machine bus ( ) through several translation stages and multiplexers. The decision of which source to use is based on what kind of instruction is currently being looked at by the instruction queue in the instruction fetch unit. The instruction queue notifies the instruction decoder that the next instruction is to be either a RISC operation (including register, memory, and/or branch instructions) or an instruction which is part of a microcode flow. If a complex macroinstruction flow is in progress, its operands can be accessed through alias registers. This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic ( ).

Apparatus for issuing instructions and reissuing a previous instructions by recirculating using the delay circuit

A microprocessor comprised of Instruction Fetch Unit (10), Instruction Decoder (12), Pipeline Sequencer (14), Register File (16), Multiply/Divider-Unit, Execution Unit, and REG coprocessors block (18) and instruction cache, Address Generation Unit, local register cache, and MEM coprocessors block (20). The Instruction Cache provides the Instruction fetch unit (10) with instructions every cycle. The instruction sequencer (IS) includes the Fetch Unit (IFU-10), the Instruction Decoder (ID-12) and the Pipeline Sequencer (PS-14). The instruction sequencer can decode and issue up to three instructions per clock. The pipe sequencer (14) employs a write back path to store snap shots of the state of the machine in pipe stages 1 and 2. This provides the way for branch guessing and the process switching to correct itself after issuing a wrong IP (in the case of the branch guessing), or a way to preserve the internal state of the machine at the time a context switching occurs in order to come back to the same condition it had left.

Instruction pipeline sequencer in which state information of an

Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the selected word. A full adder (40) adds this displacement to the instruction pointer. The result is used as the branch address. The timing is such that a 1 clock lookahead is sufficient to hide this calculation from program execution. The branch register address is determined by the process ID and the macro mode state bit. The branch by pass mechanism causes the branch address to be driven from the calculation instead of a branch register. If a branch fail or scoreboard hit occurs, a write cancellation is generated to stop the current address calculation from being stored in a branch register. If a branch fail or scoreboard hit does not occur, then the current address calculation is stored in a branch register. If a branch bypass occurs, then the branch address is driven from the calculation. If a branch bypass does not occur, then the branch address is driven from the branch register.

Branch look ahead adder for use in an instruction pipeline sequencer

An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functional units capable of independently executing second microinstructions that take a single clock cycle to complete execution. The first and second microinstructions are issued by an instruction decoder. A microintruction bus (112) is connected to the instruction decoder, the register file, and to each of the first and second functional units. A REG interface and a destination bus (110) are also connected to the register file (6). A Scbok line (102) is connected between the instruction unit, the register file and to each one of the first and second functional units. The instruction decoder includes means for asserting the Scbok line to signal that a current microinstruction on the microintruction bus (112) is valid. Means in the register file disassert the Scbok signal upon the condition that any one register in the register file needed by the instruction on the microinstruction bus is busy. An EU write line (102) connected from one of the single cycle functional units to the multiple cycle functional units is asserted by one of the single cycle functional units upon the condition that the single cycle functional unit requests access to the destination bus. The multiple cycle functional units and single cycle functional units are connected to the REG interface and to the destination bus. Arbitration means (3) in each of the multiple cycle functional units respond to the EU write line and to the Scbok line to prevent access to the destination bus upon the condition that the EU write line and the Scbo k line are asserted.

Interface between a register file which arbitrates between a number of

A hierarchical memory which includes a backing store read/write memory (18) for storing first words, and a read-only memory RAM (60) for storing frequently used words. The buffer store has two parts, a cache RAM (64) and a two-word queue (62) comprised of two fetch buffers. The cache RAM is provided for storing a copy of some of the word stored in the backing store in accordance with a use algorithm. The ROM, queue buffers and cache RAM are simultaneously searched to see if the address for requested words is in either of them. If not, a fetch (76) is made of the backing store (18) and the words are written into the fetch buffers. The next time that address is presented, the fetch buffers are written into the cache and simultaneously read out to the bus. A first Y-mux (63) is provided between the ROM and the cache RAM for multiplexing the appropriate ROM columns to drive the Cache RAM bit lines directly when an internal micro-address is selected. The word positions within a row of the ROM are so ordered as to enable multiple words to be read out simultaneously regardless of what starting address is presented to the ROM. A second Y-mux (67) is provided between the cache RAM and the bus (19) for multiplexing the multiple words. The second Y-mux is controlled by at least one bit of the internally selected address. A multiplexer (74) is connected to the second Y-mux for shifting its input an appropriate amount according to bits of the starting address, such that the correct words are read out in the correct position.

High bandwith output hierarchical memory store including a cache, fetch

A microprocessor having a memory coprocessor (10) connected to a MEM interface (16) and a register coprocessor (12) connected to a REG interface (14). The REG interface (14) and MEM interface (16) are connected to independent read and write ports of a register file (6). An Instruction Sequencer (7) also connected to an independent write port of the register file, to the REG interface and to the MEM interface. An Instruction Cache (9) supplies the instruction sequencer with at least two instruction words per clock (7). Single-cycle coprocessors (4) are connected to the REG interface (14) and a multiple-cycle coprocessors (2) are connected to the REG interface (14). An Address Generation Unit (3) is connected to the MEM interface (16) for executing load-effective-address instructions and address computations for loads and stores to thereby perform effective address calculations in parallel with instruction execution by the single-cycle coprocessor. The Instruction Sequencer (7) decodes incoming instruction words form the Cache, and issues up to three instructions on the REG interface (14), the MEM interface (16), and/or the branch logic within the Instruction Sequencer. The instruction sequencer includes means for detecting dependencies between the instructions to thereby prevent collisions between instructions. A local register cache (5) is provided connected to the MEM interface. The local register cache maintains a stack of multiple word local register sets, such that one each call the local registers are transferred from the register file (6) to the Local Register Cache (5) to thereby allocate the local registers in the register file for the called procedure and on a return the words are transferred back into the register file to the calling procedure.

Microprocessor in which multiple instructions are executed in one clock

An aliasing logic (100) in an instruction decoder. If a complex microinstruction flow is in progress, it operands can be accessed through alias registers (116). This allows indirect access to a source or destination register specified by the operands of the macrocode instruction or the opcode of the macroinstruction while executing a sequence of microinstructions. These aliased operands are maintained by the macroinstruction aliasing logic (100) in the register (116). The instruction decoder issues new instructions by driving a machine bus (110) with the correct information during each clock cycle. Mousetrap multiplexer (104) chooses between several sources of opcode and operand fields and routes the them to the machine bus (110) through several translation stages and multiplexers.

Method of modifying a microinstruction with operands specified by an

A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory interface unit. Each unit connected to the scbok line can pull the line to indicate that it is busy. Each unit connected to the mem scbok line can pull the line to indicate that it is busy. The scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a register file operation. The mem scbok line indicates, when asserted, that a unit or a register in the register file that is busy with a previous instruction is not available to an instruction for a memory operation. Registers are checked concurrently with the issuing of an instruction. An instruction lacking any needed unit or a register is stopped in response to the asserted scbok line and reissued in the next cycle. Registers to be used by a multi-cycle instruction are marked busy for an instruction that is able to be executed. When a result for the multi-cycle instruction returns the registers previously marked busy are marked as not busy.

System for executing different cycle instructions by selectively

A random access memory cell in a register file having multiple independent read ports and multiple independent write ports that support parallel instruction execution. The RAM cell consumes low power and conforms to a tight layout pitch to meet the needs of the random access memory. A single column line is used, with the storage latch device (M 11, M 12) increased in size to provide for the noise margin loss with reference to the prior art two-column design. A single n-device (M 1) is attached to the opposite side of the cell latch (M 11, M 12) to clear the cell prior to writing zeros into the cell. The registers that are to be written are first cleared in the PH2 of the first clock cycle, with the data written in PH1 of the second clock cycle which writes the ones. The zero bits are also written at this time, but they find a cell that already is in the zero state, having been cleared in PH2 of the first clock cycle.

Growing community of inventors

Chandler, AZ, United States of America

Frank S Smith