International Business Machines Corporation

Globalfoundries Inc.

Toppoly Optoelectronics Corporation

Kyocera Corporation

Chi Mei Optoelectronics Corporation

Frank Robert Libsch

Russell Alan Budd

Ghavam G Shahidi

Devendra K Sadana

Stephen W Bedell

Ning Li

Bing Dang

Paul Stephen Andry

Robert L Wisnieff

James Lawrence Sanford

Venkat K Balagurusamy

Gareth Geoffrey Hougham

Seiji Munetoh

Eric Vance Kline

Daniel Joseph Friedman

Fuad Elias Doany

Stephen Mark Rossnagel

Ko-Tao Lee

Kai R Schleupen

Punit P Chiniwalla

Jeonghwan Song

Chung H Lam

Vijay Narayanan

Jae-Woong Nah

Dirk Pfeiffer

Ramachandran Muralidhar

Eduard Albert Cartier

Xiao Hu Liu

Richard Harold Boivie

Sung Kwon Kang

Paul Francis Fortier

Gerard McVicker

Shui-Chih Alan Lien

Kohji Hosokawa

Charanjit Singh Jutla

Xiaoxiong Gu

Wanki Kim

Chandrasekara Kothandaraman

Philip C D Hobbs

Tak H Ning

Ali Afzali-Ardakani

Paul William Coteus

Cheng-Wei Cheng

Kuen-Ting Shiu

James Bowler Hannon

Thomas S Mazzeo

Kei-Hsiung Yang

Uzma B Rana

Robert J Polastre

Michael Patrick Mastro

Leslie C Jenkins

Robert Wayne Nywening

Venkat K Belagurusamy

Evan G Colgan

Cyril Cabral, Jr

Brian Samuel Beaman

Benjamin V Fasano

Chitra K Subramanian

Takatoshi Tsujimura

Shawn Anthony Hall

Benjamin G Lee

Theron Lee Lewis

David Hirsch Danovitch

Chirag Suryakant Patel

Alphonso Philip Lanzetta

Daniel Peter Morris

Nicolas Dupuis

Luc Gilbert Guerin

Hiroaki Kitahara

Eugene S Schlig

Sylvain E Ouimet

Peter M Fryer

Arun Paidimarri

Abhilash Narendra

Amanda E E Mikhail

Kathleen Conlon Hinge

Hisanori Kinoshita

John S Corbin

Tsujimura Takatoshi

Paul Fortier

An impedance sensing structure is provided and includes a dielectric layer, a spiral electrode pair forming a dual spiral channel on the dielectric layer and having an inlet portion at a central region of the dual spiral channel and an outlet portion at an end of the dual spiral channel, inlet and outlet elements and sensing circuitry. The inlet and outlet elements are coupled with the inlet and outlet portions, respectively, for directing fluid or gas to flow through the dual spiral channel. The sensing circuitry is electrically connected with the spiral electrode pair and configured to sense the particles in the fluid or gas in accordance with an impedance of the spiral electrode pair and the fluid or gas flowing through the dual spiral channel.

Spiral impedance structure

A sensing structure is provided and includes a tubular element through which a fluid is flowable along a single path, an array of sensors disposed along a length of the tubular element whereby the fluid is flowable through each of the sensors and sensing circuitry electrically connected with each of the sensors and configured to measure a reactance of each of the sensors and to determine whether any reactance is indicative of a presence of a biological cell in the fluid flowing through the corresponding sensors.

Linear fluidic cell trap device for single cell detection

A 2D microfluidic structure for capacitance sensing of analyte is provided. The structure includes a first substrate located above at least one microfluidic channel, and a second substrate located below the at least one microfluidic channel. The first substrate includes at least one first group of three isolated electrodes and the second substrate includes at least one second group of three isolated electrodes, where each group of isolated electrodes includes a ground electrode and two probe electrodes.

2D microfluidic structure

Compound semiconductor and silicon-based structures are epitaxially formed on semiconductor substrates and transferred to a carrier substrate. The transferred structures can be used to form discrete photovoltaic and light-emitting devices on the carrier substrate. Silicon-containing layers grown on doped donor semiconductor substrates and compound semiconductor layers grown on off-cut semiconductor substrates form elements of the devices. The carrier substrates may be electrically insulating substrates or include electrically insulating layers to which photovoltaic and/or light-emitting structures are bonded.

Device integration using carrier wafer

An interconnect for a semiconductor device includes: a carrier; a UV programmable chip mounted on the carrier using a first array of solder connections; a UV light source mounted on the carrier using a second array of solder connections, the UV light source being in optical communication with the UV programmable chip; and a plurality of transmission lines extending on or through the carrier and providing electrical communication between the UV programmable chip and the UV light source.

Dense hybrid package integration of optically programmable chip

A processor-implemented method imposes trust at the edge of a blockchain. A hardware interrogator in a terminal interrogates an Internet of Things Smart Device (IoTSD). The IoTSD is an off-line device that is associated with a physical product. The IoTSD includes a cryptographic processor and one or more state sensors that monitor a state of the physical product. The hardware interrogator detects an event that is described by an encrypted entry in the IoTSD. The terminal transmits, to a blockchain, a transaction that describes the event that is detected by the hardware interrogator, such that the blockchain adds the transaction to a blockchain that is dedicated to the physical product, and the blockchain establishes a state of the physical product.

Smart device to impose trust at the edge of a blockchain

Attach a smart chip to a carrier, and attach a memory chip to the carrier in communication with the smart chip. The memory chip has a larger footprint than the smart chip, overlies the smart chip, and is attached to the carrier by connections around the periphery of the smart chip. Removably attach an energy storage device (ESD) to the carrier and electrically connect the ESD to the carrier via a flex bridge.

Tetherless chip module

A tetherless system-in-package includes a first integrated circuit (IC) chip having interconnects and energy harvesting elements. A super-capacitor is configured to store a charge output by the energy harvesting elements. At least a second IC chipset including a smart chip and an optical I/O or an RF I/O is aligned and bonded to at least one of the interconnects of the first IC chip. The first IC chip and the second IC chip are configured to receive a portion of the charge stored by the super-capacitor.

Battery-free and substrate-free IoT and AI system package

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.

Radio frequency identification based integrated computer with hardware accelerator

A capacitive sensor array for in-situ monitoring directed self-assembly of a self-assembling material is provided. The capacitive sensor array includes a bottom electrode plate including a plurality of bottom electrodes that are spaced apart and electrically isolated from one another, template structures located on the bottom electrode plate, wherein the template structures define trenches therebetween, each of the trenches exposing at least one of the plurality of bottom electrodes; and a top electrode plate assembled on the bottom electrode plate, wherein the top electrode plate includes a plurality of top electrodes that are spaced apart and electrically isolated from one another, the top electrodes facing and intersecting, but electrically isolated from, the bottom electrodes.

Structure and method for monitoring directed self-assembly pattern formation

A silicon chip carrier includes at least two of a photosensitive P-I-N diode, a non-photosensitive P-I-N diode, a photosensitive P-(metal)-N diode, a non-photosensitive P-(metal)-N diode, and a Schottky diode all integrally formed in the same layers of the chip carrier. In some embodiments, diodes formed in the chip carrier provide photovoltaic power and power regulation to a circuit mounted on the chip carrier.

Chip carrier integrating power harvesting and regulation diodes and fabrication thereof

A hard mask and a method of creating thereof are provided. A first layer is deposited that is configured to provide at least one of a chemical and a mechanical adhesion to a layer immediately below it. A second layer is deposited having an etch selectivity that is faster than the first layer. A third layer is deposited having an etch selectivity that is slower than the first and second layers. The third layer has a composite strength that is higher than the first and second layers. A photoresist layer is deposited on top of the third layer and chemically removed above an inner opening. The third layer and part of the second layer are anisotropically etched through the inner opening. The second layer and the first layer are isotropically etched to create overhang regions of the third layer.

Self-aligned, over etched hard mask fabrication method and structure

An energy storage device for an integrated circuit carrier package. One or more energy storage elements have contact elements arranged thereon that include an anode, a cathode, and an isolated common pad. The energy storage element is configured for arrangement in a stack of energy storage elements in which the isolated common pad is shorted to one of the anode or the cathode by bonded conductive interconnects.

IoT and AI system package with solid-state battery enhanced performance

A solid state electrochemical battery fabrication device and a method of creating the solid state electrochemical battery are provided. There is a first chamber comprising a first magnetron and a second chamber comprising a second magnetron, coupled to the first chamber. There is a third chamber comprising a vapor source for a polymer deposition, coupled to the second chamber. A Knudsen cell is coupled to the third chamber and configured to deposit lithium on a battery being fabricated. A linear hollow shaft connects the first, second, and third chambers, and provides a hermetic seal. A first telescopic arm having a housing is coupled to a first end of the hollow shaft and configured to extend out of its housing from the first chamber to the second chamber.

Tool and method of fabricating a self-aligned solid state thin film battery

Growing community of inventors

White Plains, NY, United States of America

Frank Robert Libsch