Inphi Corporation

Cortina Systems Corporation

Research in Motion Corporation

Huawei Technologies Co., Limited

Frank Robert Kschischang

Arash Farhoodfar

Benjamin P Smith

Andrew Hunt

Stewart N Crozier

Ramesh Mantha

John Lodge

Deyuan Chang

Yoones Hashemi Toroghi

Chunpo Pan

A multidimensional multilevel coding (MLC) encoder comprises a soft forward error correction (FEC) encoder receiving first bits for generating soft FEC encoded bits, a redundancy generator receiving a subset of the soft FEC encoded bits for generating redundant bits, and a hard FEC encoder receiving second bits for generating hard FEC encoded bits. Combinations of the soft FEC encoded bits, the redundant bits, and the hard FEC encoded bits form labels for mapping to a plurality of constellation points. A MLC decoder comprises a redundancy decoder, a soft FEC decoder and a hard FEC decoder. The redundancy decoder combines log-likelihood-ratios (LLR) of soft FEC encoded bits received from the MLC encoder to allow the soft FEC decoder to produce decoded bits. Decoding of hard FEC encoded bits by the hard FEC decoder is conditioned on values of the bits decoded by the soft FEC decoder.

Multidimensional multilevel coding encoder and decoder

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Time varying data permutation apparatus and methods

For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

Apparatus and method for communicating data over a communication channel

For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40 G/100 G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.

In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks B, a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bin the sequence are computed. The coding symbols are computed such that, for each symbol block Bthat has a preceding symbol block Band a subsequent symbol block Bin the sequence, symbols at symbol positions along one dimension of the preceding symbol block B, concatenated with the data symbols and the coding symbols along the other dimension in the symbol B, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol B, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B, form a codeword of the FEC component code. Thus, each row in [BB] and each column in for example, is a valid codeword.

Staircase forward error correction coding

In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks B, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bin the sequence are computed. The coding symbols are computed such that, for each symbol block Bthat has a preceding symbol block Band a subsequent symbol block Bin the sequence, symbols at symbol positions along one dimension of the preceding symbol block B, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block B, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block B, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block B, form a codeword of the FEC component code. Thus, each row in [BB] and each column in for example, is a valid codeword.

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Mississauga, Canada

Frank Robert Kschischang