Infineon Technologies Ag

Globalfoundries Inc.

Frank Richter

Dietmar Temmler

Frank Seliger

Andreas Wich-Glasen

Stephan Kronholz

Markus Lenski

Thomas Werner

Jens Heinrich

Martin Popp

Herbert Benzinger

Valentin Rosskopf

Gunda Beernink

Guenther Gerstmeier

Dieter Temmpler

When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.

Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material

In a replacement gate approach, a top area of a gate opening has a superior cross-sectional shape which is accomplished on the basis of a plasma assisted etch process or an ion sputter process. During the process, a sacrificial fill material protects sensitive materials, such as a high-k dielectric material and a corresponding cap material. Consequently, the subsequent deposition of a work function adjusting material layer may not result in a surface topography which may result in a non-reliable filling-in of the electrode metal. In some illustrative embodiments, the sacrificial fill material may also be used as a deposition mask for avoiding the deposition of the work function adjusting metal in certain gate openings in which a different type of work function adjusting species is required.

Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition

A memory cell includes a selection transistor and a trench capacitor. The trench capacitor is filled with a conductive trench filling on which an insulating covering layer is arranged. The insulating covering layer is laterally overgrown, proceeding from the substrate with a selectively grown epitaxial layer. The selection transistor is formed in the selectively grown epitaxial layer, comprises a source region connected to the trench capacitor and a drain region connected to a bit line. The junction depth of the source region is chosen so that the source region reaches as far as the insulating covering layer. Optionally, the thickness of the epitaxial layer can be reduced to a thickness by oxidation and a subsequent etching. Afterwards, a contact trench is etched through the source region down to the conductive trench filling, which trench is filled with a conductive contact and electrically connects the conductive trench filling to the source region.

Dram memory cell with a trench capacitor and method for production thereof

The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow Ican be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current I. The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

Field effect transistor and method for fabricating it

The present invention relates to a memory cell arrangement and a fabrication method for this memory cell arrangement. In this case, the memory cells ( ) arranged regularly on a semiconductor wafer each have a trench capacitor ( ) formed in the semiconductor substrate ( ), and a selection transistor ( ) formed above the trench capacitor ( ), and also a self-aligned selection transistor ( )&mdash;memory trench contact ( )&mdash;trench insulation ( ) arrangement.

Memory cell arrangement and method for its fabrication

A DRAM cell configuration is described in which a memory cell in each case has a storage capacitor and a read-out transistor. For connecting to the read-out transistor, a buried strap contact is produced by outdiffusion of dopants from the electrode of the storage capacitor. The buried strap contact is superposed by the implantations of the source/drain region of the read-out transistor, so that the implantations of the source/drain region form the boundary of the space charge zone of a p/n junction of the memory cell.

DRAM cell configuration and method for fabricating the DRAM cell configuration

In a method for examining structures on a wafer, at least one mask, which is applied on the wafer and is fabricated by exposure processes, is used for fabricating the structures. Test circuits with test structures are placed on the mask in predetermined reference positions. In order to check the structures and/or the exposure processes, electrical parameters of the test circuits are detected and evaluated in a location-dependent manner.

Method for examining structures on a wafer

With increasing integration density of integrated circuits, the packing density in test regions (kerf structures) located between the integrated circuits cannot be increased substantially, since the majority of the available area is occupied by contact areas. The invention is therefore directed toward a test structure region on a wafer having contact areas for applying voltages and test components between the contact areas. The test structure includes at least two test components that are arranged between two adjacent contact areas. The test components are each connected to the adjacent contact areas so that a voltage can be applied to the test components via the contact areas.

Test structure in an integrated semiconductor

A simple method for fabricating a field-effect transistor having an anti-punch-through implantation region is provided. After the anti-punch-through implantation region is formed, a semiconductor substrate is locally oxidized by using a mask layer in order to form a gate insulation layer. The method allows the fabrication of field-effect transistors having improved short-channel properties.

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Dresden, Germany

Frank Richter